Summary
IEICE Information and Communication Technology Forum
2014
Session Number:MOBILE2
Session:
Number:MOBILE2-4
100 Gbps Wireless - Challenges to the data link layer
Lukasz Lopacinski, Marcin Brzozowski, Rolf Kraemer, Joerg Nolte,
pp.-
Publication Date:2014-08-10
Online ISSN:2188-5079
DOI:10.34385/proc.19.MOBILE2-4
Summary:
The design of high speed wireless networks is a challenging task. In this paper, basic problems of an implementation of a 100 Gbps parallel data link layer processor are discussed. Such a high data rate requires a fast and low latency memory for Automatic Repeat reQuest (ARQ). Two popular memory types were investigated. Use of a DDR3 memory may lead to too long latencies, while use of a Field Programmable Gates Array (FPGA) on chip block RAM memory requires a wide memory bus and has the problem that the memory size is limited. Forward Error Correcting Codes (FEC) algorithms have to be chosen very carefully because of complexity issues. A complicated FEC may lead to huge structures and thus hardware overhead (more than 20 Virtex7 FPGAs). Even with less complicated FEC, there is probably a need to use multiple FPGAs and fast interconnect interfaces between them. For this reason high speed serial input-output transceivers are introduced. Another problem is the installation of such a network interface card in a PC system; all introduced high speed development kits did not support a bandwidth of 100 Gbps for PCI express.