FPGA implementation of parallel routing algorithm for three-stage Clos networks with component switch sizes of a power of two

Koloko Labson; Hitoshi Obara

Summary

International Conference on Emerging Technologies for Communications

2020

Session Number:D2

Session:

Number:D2-1

FPGA implementation of parallel routing algorithm for three-stage Clos networks with component switch sizes of a power of two

Koloko Labson, Hitoshi Obara,

pp.-

Publication Date:2020/12/2

Online ISSN:2188-5079

DOI:10.34385/proc.63.D2-1

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Summary:

A fast parallel algorithm for setting up three-stage Clos networks, in which the component switch sizes have a power of two, is presented. The algorithm is implemented on an FPGA, and its performance is evaluated through experiments. It is found that the algorithm can operate as fast as the time complexity of O(logN) up to a certain Clos switch size of N. In contrast, conventional algorithms require a time complexity of at least O((logN)^2).