Summary
International Symposium on Nonlinear Theory and Its Applications
2022
Session Number:B4L-D
Session:
Number:B4L-D-01
Subthreshold CMOS Bistable Circuit for Stochastic Memory Device
Seiya Muramatsu , Kohei Nishida , Kota Ando , Megumi Akai-Kasaya , Tetsuya Asai,
pp.405-408
Publication Date:12/12/2022
Online ISSN:2188-5079
Summary:
One of the problems in stochastic computing is the high cost of memory utilization. To solve this problem, we propose a bistable circuit and a parallel shift circuit to realize stochastic memory. The bistable circuit forms a double-well potential using the subthreshold characteristics of MOSFETs, and the output voltage is stabilized at two values. The parallel shift circuit shifts the potential left and right in parallel by the gate voltage of a floating-gate MOSFET. In SPICE simulation, the probability of the output bit sequence is shown to vary with the floating gate voltage.