Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:D2
Session:
Number:D2-2
Design and Analysis of On-chip Leakage Monitor using an MTCMOS circuit
Satoshi Koyama, Seidai Takeda, Kimiyoshi Usami,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
Leakage current varies drastically due to process variation and temperature changes. At the circuit design stage, it is difficult to estimate the amount of leakage current at every manufactured chip. The Virtual-ground (VGND) voltage of MTCMOS circuits increases during the sleep operation, because parasitic capacitance of the line is charged up by the leakage current. By applying this behavior, we design leakage monitor circuits using ASPLA 90nm technology. Simulation results show that monitor delay-time is 165ns and monitor-error is 6% under the typical process condition, 25°C and operating frequency of 200MHz.