Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:T2-2
Session:
Number:4784
A 1V/1.8V Ultra Low Noise LDO for 5.6GHz PLL Applications
Thi Kim Nga Truong, Hamed Abbasizadeh, Sung-Hun Cho, Dong-Soo Lee, Kang-Yoon Lee ,
pp.495-497
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
This paper presents a low noise low drop voltage (LDO) for 5.6GHz PLL application. The proposed LDO employs internal RC-Filter with multi-layer capacitor at the output of the bandgap reference (BGR) to achieve ultra-low noise at interest frequencies. It is also a mode changeable LDO so that the output voltage level can be 1V/1.8V. The 4-bits controlled resistor ladder is adopted to compensate the process voltage temperature (PVT) variation. The highest output noise of the LDO are 5.68fV2/Hz and 23fV2/Hz at 10 kHz in 1V/1.8V mode respectively. The proposed LDO is implemented in CMOS 65nm technology with the die size is 460um x 290um.