Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2016
Session Number:T1-2
Session:
Number:4417
A Ratio-insensitive Switched-Capacitor Algorithmic Digital-to-Analog Converter Using Sample/Hold and Divider
Hiroki Matsumoto ,
pp.423-426
Publication Date:2016/7/10
Online ISSN:2188-5079
Summary:
A novel switched-capacitor algorithmic digital-to-analog (D/A)converter using sample/hold and divider is described. The operation is insensitive to capacitor mismatch. Thus, accurate D/A conversion is possible on standard CMOS process technology. Accuracy estimation shows that 15 bit resolution is possible on capacitor mismatch of 1 percent.