Summary
the 2014 International Symposium on Nonlinear Theory and its Applications
2014
Session Number:A1L-E
Session:
Number:A1L-E3
Dual-Rail Asynchronous Pipeline Based on Stochastic Resonance Logic Gates
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura,
pp.85-88
Publication Date:2014/9/14
Online ISSN:2188-5079
Summary:
This study proposes an application of stochastic resonance logic gates (SR logic gates), proposed by Asai etal. These gates generate basic logic functions in which noise plays an important role in recovering logic operations in the presence of mismatches among devices. These gates work at low power consumption regardless mismatches in comparison with conventional gates. However, one limitation is the timing response, because it is dependent on stochastic processes. Therefore, we propose the design of asynchronous circuits as a suitable application for SR logic gates. In this study, we demonstrate the performance of a three-stage asynchronous pipeline with a dual-rail data encoding. Simulations were performed for a 0.18-μm CMOS technology in SPICE. The simulations show that even in the presence of unpredictable delays, the pipeline successfully accomplishes data transmission. Moreover, experimental results are also shown employing a macro system.