Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:P2
Session:
Number:P2-5
A High-Level Power Estimation Methodology for Low Power Design
Chi-Ho Lin,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
This work is a contribution to high-level synthesis for low power systems. In this paper, we present an efficient algorithm on performing estimation with an aim of reducing the power consumption in the synthesized data path. In this paper, CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, The power estimation methods on enable power management and module selection are performed, so as to reduce the power consumption in low power design. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.