International Technical Conference on Circuits/Systems, Computers and Communications


Session Number:M1-6



FPGA Implementation of Miller Line Encoding to Prevent Stuff Bits in CAN for Jitterless Communication

Ronnie Opone Serfa Juan,  Min Woo Jeong,  Hi Seok Kim ,  


Publication Date:2016/7/10

Online ISSN:2188-5079


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Controller Area Network protocol utilizes Non Return-to-Zero (NRZ) line encoding, but long runs of consecutive bits with the same signal level may cause problems in transmission. Adding stuff bits can force the synchronization, however, it reduces the frame rate and causes jitter in communication. The main objective of this paper is to minimize or totally prevent the usage of stuff bits that causes jitter in CAN communication. Miller Line Encoding minimizes these drawbacks. The proposed scheme is synthesized on the Xilinx Virtex-5 FPGA. The results show that the Miller Line Encoding is better than the original line encoding.