Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:D1
Session:
Number:D1-4
A Power-Saving 1GBPS Irregular LDPC Decoder based on High-Efficiency Message-Passing
Wenming Tang, Wen Ji, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
In this paper we proposed a partially-parallel decoder for irregular LDPC codes from IEEE802.11n standards. Our proposed decoder adopts high-efficiency message-passing algorithm and uses the min-sum algorithm handle the message-passing to reduce the hardware implementation complexity and area, and keep high throughput. Considering reducing the power consumption, we used half-registers and half-memory to store the temporary intrinsic messages. The wasted motion of shift-register was suppressed. This strategy would save us higher as 30% power under good channel condition. The synthesis result in TSMC 0.18um COMS technology demonstrated that for (1296,324) irregular LDPC code achieved high throughput (1.05Gbps) at the frequency of 200MHz, with 6% area reduction.