Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:G1
Session:
Number:G1-3
Complex Multiplier Suited for FPGA Structure
Keiichi Satoh, Jubee Tada, Kenta Yamaguchi, Yasutaka Tamura,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
In this paper, we propose complex multiplier suited for FPGA structure to achieve higher performance and lower cost. The complex multiplier is based on LUT (Look-Up-Table) and carry-chain from FPGA structure, we utilize Booth algorithm for partial product generation and Wallace tree utilizing effectively LUTs and carry-chains in the FPGA structure for the partial products compression to design it. We design Wallace trees of various types utilizing LUTs and carry-chains, the complex multipliers implemented the trees are synthesized by synthesis tool. Consequently, the proposed complex multipliers are superior to one synthesized by operator ('*','+', and '-') from VHDL description for both the path delay and the scale.