Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:D5
Session:
Number:D5-5
An Efficient Implementation of Multi-channel H.264 Decoder SoC
Wonjong Kim, Juneyoung Chang, Hanjin Cho,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
We developed a multi-channel H.264 decoder based on a single channel H.264 decoder which was developed using autonomous module design methodology. Since an autonomous module can control itself by checking states of its neighbor modules, we could easily extend the decoder for decoding multi-channel streams. We utilized the nature of SDRAM structure for efficient use of frame data. We developed specialized SDRAM controller and DMA controller for efficient data transfers of 2-dimensional data. By assigning dedicated channels for modules which require data transfer from/to SDRAM, they can freely use SDRAM data. The decoder can decode 1~16 channels of QVGA, 1~4 channels of VGA, 1~2 channels of XGA or HD, or 1 channel of Full-HD videos at 30 fps within 150 MHz.1