Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:D3
Session:
Number:D3-5
Development and Evaluation of Raytracing Accelerating Engine with Bit Serial Arithmetic Units
Tomoyuki Kawamoto, Kazuya Tanigawa, Tetsuo Hironaka, Yuhki Yamabe,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
Several methods of parallel computing for high speed processing for raytracing with hardware were proposed. But, the chip of conventional raytracing hardware needs huge area by using parallel arithmetic units. In this paper, we present a design of a raytracing accelerator engine with bit serial arithmetic unit to decrease chip area and improve the performance. As the first stage, we designed prototype hardware which calculate only the process of highest load ratio in processing elements, and evaluate it. As a result, the prototype hardware was about 5.09 times faster within same chip area.