Summary
International Technical Conference on Circuits/Systems, Computers and Communications
2008
Session Number:D2
Session:
Number:D2-3
A Multi-thread Processor Architecture With Dual Phase Variable-Length Instructions
HyungKi Jeong, KwangYeob Lee, Jae-Chang Kwak,
pp.-
Publication Date:2008/7/7
Online ISSN:2188-5079
Summary:
Most of multimedia processors for 2D/3D graphics acceleration uses a lots of integer/floating point arithmetic units. We present a new architecture that has more small chip size, performs effective ALU using and reduces instruction cycles significantly with a foundation of multi-thread operation, variable length instruction words, dual phase operation and phase instruction's coordination theories.