Summary
Asia-Pacific Conference on Communications
2008
Session Number:16-AM2-B
Session:
Number:1569126315
A Simplified Addition Operation Log-SPA LDPC Decoder
Po-Hui Yang, Jung-Chieh Chen, Ya-Ting Chan, Ming-Yu Lin,
pp.-
Publication Date:2008/10/14
Online ISSN:2188-5079
DOI:10.34385/proc.27.1569126315
Summary:
A low hardware cost Low-Density Parity-Check (LDPC) decoder is presented in this paper. Using logical OR operation in the check nodes for the log sum-product algorithm (Log-SPA), we propose a new architecture for updating the check nodes messages. Synthesized and numerical results show that the proposed architecture achieves up to 21% total hardware reduction with fair BER performance when compared with the traditional Log-SPA decoder. Moreover, the proposed decoder also outperforms the simplest known sign-min architecture in terms of hardware complexity and BER performance.