Information and Systems-Reconfigurable Systems(Date:2015/09/18)

A High-level Hardware Design Environment in Python

Shinya Takamaeda(NAIST),  

[Paper #]RECONF2015-36

Naru Sugimoto(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Paper #]RECONF2015-39
A Design of Basic Functions and Forced Play of TRAX Game for FPGA with High-Level Synthesis Tool

Tomonori Izumi(Ritsumeikan Univ.),  Masashi Ono(Ritsumeikan Univ.),  Yuuya Hiroe(Ritsumeikan Univ.),  Lin Meng(Ritsumeikan Univ.),  

[Paper #]RECONF2015-32
Trax solver based on machine-learned evaluation function

Takuya Nakamichi(Kumamoto Univ.),  Yusuke Sonoda(Kumamoto Univ.),  Takayuki Matsuzaki(Kumamoto Univ.),  Motoki Amagasaki(Kumamoto Univ.),  Masahiro Iida(Kumamoto Univ.),  Morihiro Kuga(Kumamoto Univ.),  Toshinori Sueyoshi(Kumamoto Univ.),  

[Paper #]RECONF2015-33
Design of Hardware Description Language FSL Based on Object-Oriented/Functional Programming Languages

Nobuya Watanabe(Okayama Univ.),  Akira Nagoya(Okayama Univ.),  

[Paper #]RECONF2015-37
[Invited Talk] Measurements and Optimal Controls of Plant Responses based on a SPA (Speaking Plant Approach)

Tetsuo Morimoto(Ehime Univ.),  

[Paper #]RECONF2015-41
Comparison of machine learning classifiers for HOG-based human detection on an FPGA

Masahito Oishi(Nagasaki Univ.),  Yoshiki Hayashida(Nagasaki Univ.),  Ryo Fujita(Nagasaki Univ.),  Yuichiro Shibata(Nagasaki Univ.),  Kiyoshi Oguri(Nagasaki Univ.),  

[Paper #]RECONF2015-34
Overview of the Reconfigurable Virtual Accelerator ReVA

Hironori Nakajo(TUAT),  Yuki Oigo(TUAT),  Shozo Takeoka(AXE),  Masashi Takemoto(BeatCraft),  Takefumi Miyoshi(Wasalabo),  

[Paper #]RECONF2015-40
Empirical evaluation of an arithmetic design approach with diversity and redundancy for FPGAs

Yudai Shirakura(Nagasaki Univ.),  Kenichi Morimoto(Nagasaki Univ.),  Masanori Nobe(MHPS),  Masaharu Tanaka(MHI),  Yuichiro Shibata(Nagasaki Univ.),  Hidenori Maruta(Nagasaki Univ.),  Fujio Kurokawa(Nagasaki Univ.),  

[Paper #]RECONF2015-38
[Invited Talk] Game Tree Search Techniques and its Application to Computer Shogi

Shogo Takeuchi(Hokkaido Univ.),  

[Paper #]RECONF2015-35
A Design Method Using Discrete Particle Swarm Optimization for a Deep Neural Network Based on Nested RNS

Tatsuya Ogawa(Ehime Univ.),  Hiroki Nakahara(Ehime Univ.),  Tsutomu Sasao(Meiji Univ.),  

[Paper #]RECONF2015-44
Recovery method of radiation-damaged optically reconfigurable gate arrays

Tomoya Akabe(Shizuoka Univ.),  Minoru Watanabe(Shizuoka Univ.),  

[Paper #]RECONF2015-43
Proposal of small reconfigurable device SePLD using selector

Keisuke Yamamoto(Hiroshima City Univ.),  Kazuya Tanigawa(Hiroshima City Univ.),  Tetsuo Hironaka(Hiroshima City Univ.),  Takashi Ishiguro(Taiyo Yuden),  

[Paper #]RECONF2015-42
An Implementation of AND-EXOR Programmable Logic Arrays Using FPGA primitives

Takahiro Shinohara(Ehime Univ.),  Hiroki Nakahara(Ehime Univ.),  Tsutomu Sasao(Meiji Univ.),  

[Paper #]RECONF2015-45
An Approach with DSL for Building up FPGA Primitives

Takefumi Miyoshi(WasaLabo/e-tress),  Satoshi Funada(e-trees),  

[Paper #]RECONF2015-46