IEICE Technical Committee

Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1996/12/13)

Presentation

表紙

[Date]1996/12/13
[Paper #]

Efficient Loop-folding Schduling by using Two Different Hardware Cost Estimations

S.J. MOON, K. HARASHIMA, K. FUKUNAGA,

[Date]1996/12/13
[Paper #]VLD96-65,CPSY96-77

A Novel Coding Technique for Genetic Placement Method

Naoshi NAKAYA, Akinori KANASUGI, Hiroyuki SHINDO, Mititada MORISUET,

[Date]1996/12/13
[Paper #]VLD96-66,CPSY96-78

Delay optimization considering wire resistance

Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emura,

[Date]1996/12/13
[Paper #]VLD96-67,CPSY96-79

An Algorithm to Determine the Positions of Fictitious Terminals for a Parallel Detailed Router

Atsushi Kamoshida, Shuji Tsukiyama,

[Date]1996/12/13
[Paper #]VLD96-68,CPSY96-80

Acceleration of high-level simulation by parallelization of descriptions

Minoru SHOJI, Fumiyasu HIROSE,

[Date]1996/12/13
[Paper #]VLD96-69,CPSY96-81

Formal Verification for Hardware Structure by Higher Order Predicate Logic

Kazuya SUZUKI, Takeo YOSHIDA, Yukiya MIURA,

[Date]1996/12/13
[Paper #]VLD96-70,CPSY96-82

Partial Extraction of Equivalent State Pairs for Optimizing Large Sequential Circuits

Hiroyuki HIGUCHI, Yusuke MATSUNAGA,

[Date]1996/12/13
[Paper #]VLD96-71,CPSY96-83

Power-Pro : Programmable Power Management Architecture

Tohru ISHIHARA, Koji KAI, Hiroto YASUURA,

[Date]1996/12/13
[Paper #]VLD96-72,CPSY96-84

Pass-transistor Logic with Low Threshold Voltage NMOS

Bu-Yeol LEE, Kazuo TAKI, Hideki TANAKA,

[Date]1996/12/13
[Paper #]VLD96-73,CPSY96-85

An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint

Masayuki YAMAGUCHI, Toshihiro NAKAOKA, Takashi KAMBE,

[Date]1996/12/13
[Paper #]VLD96-74,CPSY96-86

Synthesis of Asynchronous Sequential Circuits usiug Two-block Partition Pairs

Motonobu TONOMURA,

[Date]1996/12/13
[Paper #]VLD96-75,CPSY96-87

A Way of Organizing Pipelined Asynchronous Processors and a Master-Slave Register Enabling the Organization

Noritada KAMITA, Koki ABE,

[Date]1996/12/13
[Paper #]VLD96-76,CPSY96-88

Program Optimization on Instruction Cache at Runtime

Toshitaka MIURA, Yoichi MURAOKA,

[Date]1996/12/13
[Paper #]VLD96-77,CPSY96-89

Design and Evaluation of Real Time Video Image I/O Module of Parallel Image Understanding Machine RTA/1

Masahito AOYAMA, Hidehiko YAMAMOTO, Takashi MATSUYAMA,

[Date]1996/12/13
[Paper #]VLD96-78,CPSY96-90

Present Status and Problems of the Reconfigurable Computing Systems : Toward the Computer Evolution

Toshinori Sueyoshi,

[Date]1996/12/13
[Paper #]VLD96-79,CPSY96-91

Reconfigurable Machines: RM-I to RM-IV and Their Applications

Masahiro Numa,

[Date]1996/12/13
[Paper #]VLD96-80,CPSY96-92

A Tightly Coupled FPG/MPU System for Flexible Transport Data Processing

Toshiaki Miyazaki, Akihiro Tsutsui,

[Date]1996/12/13
[Paper #]VLD96-81,CPSY96-93

Reconfigurable System Using Multithread Control Library Implemented as Hardware

Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi,

[Date]1996/12/13
[Paper #]VLD96-82,CPSY96-94