| Presentation | 1996/12/13 Partial Extraction of Equivalent State Pairs for Optimizing Large Sequential Circuits Hiroyuki HIGUCHI, Yusuke MATSUNAGA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Computing equivalence states of sequential circuits or FSMs has several applications in the field of synthesis and verification. Symbolic traversal techniques are applicable only to medium-sized circuits because they require a lot of image computation in order to extract all the equivalent states. This paper proposes a novel technique for equivalence class computation in order to handle large circuits. The technique consists of output partitioning and partial extraction of equivalent state pairs. Partial extraction is done by targeting only single cycle equivalence and selecting state pairs to be checked. Experimental results on large ISCAS89 benchmarks show its applicability. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sequential circuit / equivalent states / state minimization / binary decision diagram |
| Paper # | VLD96-71,CPSY96-83 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 1996/12/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Partial Extraction of Equivalent State Pairs for Optimizing Large Sequential Circuits |
| Sub Title (in English) | |
| Keyword(1) | sequential circuit |
| Keyword(2) | equivalent states |
| Keyword(3) | state minimization |
| Keyword(4) | binary decision diagram |
| 1st Author's Name | Hiroyuki HIGUCHI |
| 1st Author's Affiliation | CAD Laboratory, Fujitsu Laboratories Ltd.() |
| 2nd Author's Name | Yusuke MATSUNAGA |
| 2nd Author's Affiliation | CAD Laboratory, Fujitsu Laboratories Ltd. |
| Date | 1996/12/13 |
| Paper # | VLD96-71,CPSY96-83 |
| Volume (vol) | vol.96 |
| Number (no) | 425 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |