Presentation | 1996/12/13 Acceleration of high-level simulation by parallelization of descriptions Minoru SHOJI, Fumiyasu HIROSE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | High-level simulation is faster than gate-level logic simulation, however the simulation speed is too slow for large systems. Simulation speed was accelerated for gate-level logic simulation by parallel simulation methods. However sequential statements of high-level descriptions lower the parallelism that decrease simulation speed. We developed the method to extract parallelism from high level descriptions for the acceleration of parallel simulation. We evaluated our methods utilizing CAD accelerator TP5000. By the extraction of the parallelism, the simulation speed is accelerated 7 times. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Logic simulation / High-level description / HDL / Parallelization |
Paper # | VLD96-69,CPSY96-81 |
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Conference Information | |
Committee | VLD |
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Conference Date | 1996/12/13(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Acceleration of high-level simulation by parallelization of descriptions |
Sub Title (in English) | |
Keyword(1) | Logic simulation |
Keyword(2) | High-level description |
Keyword(3) | HDL |
Keyword(4) | Parallelization |
1st Author's Name | Minoru SHOJI |
1st Author's Affiliation | FUJITSU LTD.() |
2nd Author's Name | Fumiyasu HIROSE |
2nd Author's Affiliation | FUJITSU LABORATORIES LTD. |
Date | 1996/12/13 |
Paper # | VLD96-69,CPSY96-81 |
Volume (vol) | vol.96 |
Number (no) | 425 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |