| Presentation | 1996/12/13 An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint Masayuki YAMAGUCHI, Toshihiro NAKAOKA, Takashi KAMBE, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We present an architecture evaluation system which aids designer optimizing the datapath configuration and the instruction set of embedded custom DSPs. Given a datapath structure, it evaluates the performance in terms of an estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicitly specifying the instruction format. Thus, designers can evaluate the performance of architectural variations in the early design stage. In this paper, we present details of the implementation of the evaluation system and an example of its application to an actual design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | architecture / performance evaluation / datapath structure / parallel constraint |
| Paper # | VLD96-74,CPSY96-86 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 1996/12/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Architecture Evaluation System Based on the Datapath Structure and Parallel Constraint |
| Sub Title (in English) | |
| Keyword(1) | architecture |
| Keyword(2) | performance evaluation |
| Keyword(3) | datapath structure |
| Keyword(4) | parallel constraint |
| 1st Author's Name | Masayuki YAMAGUCHI |
| 1st Author's Affiliation | Precision Technology Development Center SHARP Corporation : Dept Information Systems Eng.,Osaka University() |
| 2nd Author's Name | Toshihiro NAKAOKA |
| 2nd Author's Affiliation | Precision Technology Development Center SHARP Corporation |
| 3rd Author's Name | Takashi KAMBE |
| 3rd Author's Affiliation | Precision Technology Development Center SHARP Corporation |
| Date | 1996/12/13 |
| Paper # | VLD96-74,CPSY96-86 |
| Volume (vol) | vol.96 |
| Number (no) | 425 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |