Electronics-Integrated Circuits and Devices(Date:2013/04/04)

Presentation
表紙

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[Date]2013/4/4
[Paper #]
目次

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[Date]2013/4/4
[Paper #]
A Low Power Phase Change Memory Using Low Thermal Conductive Materials with Nano-Crystalline Structure

Takahiro MORIKAWA,  Ken'ichi AKITA,  Takasumi OHYANAGI,  Masahito KITAMURA,  Masaharu KINOSHITA,  Mitsuharu TAI,  Norikatsu TAKAURA,  

[Date]2013/4/4
[Paper #]ICD2013-1
A Novel MTJ for STT-MRAM with a Dummy Free Layer and Dual Tunnel Junctions

Koji TSUNODA,  Hideyuki NOSHIRO,  Chikako YOSHIDA,  Yuichiro YAMAZAKI,  Atsushi TAKAHASHI,  Yoshihisa IBA,  Akiyoshi HATADA,  Masaaki NAKABAYASHI,  Takashi TAKENAGA,  Masaki AOKI,  Toshihiro SUGII,  

[Date]2013/4/4
[Paper #]ICD2013-2
An Inductive-Coupling Wake-Up Transceiver for Standby Power Reduction of Non-Contact Memory Card

Noriyuki Miura,  Mitsuko Saito,  Makio Taguchi,  Tadahiro Kuroda,  

[Date]2013/4/4
[Paper #]ICD2013-3
Filament Scaling Forming Technique and Level-Verify-Write Scheme with Endurance Over 10 million Cycles in ReRAM

Akifumi Kawahara,  Ken Kawai,  Yuuichirou Ikeda,  Yoshikazu Katoh,  Ryotaro Azuma,  Yuhei Yoshimoto,  Kouhei Tanabe,  Zhigiang Wei,  Takeki Ninomiya,  Koji Katayama,  Shunsaku Muraoka,  Atsushi Himeno,  Kazuhiko Shimakawa,  Takeshi Takagi,  Kunitoshi Aono,  

[Date]2013/4/4
[Paper #]ICD2013-4
Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies

Tetsuo ENDOH,  

[Date]2013/4/4
[Paper #]ICD2013-5
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Gained Power Gating Technique : Achieves 1.0ns/200ps Wake-Up/Power-Off Times

Tetsuo ENDOH,  Takashi OHSAWA,  Hiroki KOIKE,  Sadahiko MIURA,  Hiroaki HONJO,  Keiichi TOKUTOME,  Shoji IKEDA,  Takahiro HANYU,  Hideo OHNO,  

[Date]2013/4/4
[Paper #]ICD2013-6
Fabrication of a Nonvolatile TCAM Chip Based on 4T-2MTJ Cell Structure

Shoun MATSUNAGA,  Sadahiko MIURA,  Hiroaki HONJO,  Keizo KINOSHITA,  Shoji IKEDA,  Tetsuo ENDOH,  Hideo OHNO,  Takahiro HANYU,  

[Date]2013/4/4
[Paper #]ICD2013-7
Novel Vertical Magnetization STT-MRAM Technologies for Reducing Power of High Performance Mobile Processors

Shinobu FUJITA,  Keiko ABE,  Hiroki NOGUCHI,  KITAGAWA Eiji /,  Naoharu SHIMOMURA,  Junichi ITO,  Hiroaki YODA,  

[Date]2013/4/4
[Paper #]ICD2013-8
Highly Reliable Logic Primitive Gates for Spintronics-Based Logic LSI

Y. Tsuji,  R. Nebashi,  N. Sakimura,  A. Morioka,  H. Honjo,  K. Tokutome,  S. Miura,  T. Suzuki,  S. Fukami,  K. Kinoshita,  T. Hanyu,  T. Endoh,  N. Kasai,  H. Ohno,  T. Sugibayashi,  

[Date]2013/4/4
[Paper #]ICD2013-9
Spin-Transfer Torque RAM Cache Energy Reduction Using Zero-Data Flags

Yuta Kimi,  Jinwook Jung,  Yohei Nakata,  Masahiko Yoshimoto,  Hiroshi Kawaguchi,  

[Date]2013/4/4
[Paper #]ICD2013-10
Future prospects of memory solutions for smart society : Can new nonvolatile memories replace SRAM/DRAM/Flash?

Koji NII,  Tetstuo ENDOH,  Yoshikazu KATOH,  Satoru HANZAWA,  Kazuhiko KAJIGAYA,  Atsushi KAWASUMI,  Toru MIWA,  

[Date]2013/4/4
[Paper #]ICD2013-11
Complementary atom-switch based programmable cell array and its demonstration of logic mapping synthesized from RTL code

Makoto MIYAMURA,  Munehiro TADA,  Toshitsugu SAKAMOTO,  Naoki BANNO,  Koichiro OKAMOTO,  Noriyuki IGUCHI,  Hiromitsu HADA,  

[Date]2013/4/4
[Paper #]ICD2013-12
High Performance and High Reliability 40nm Embedded SG-MONOS Flash Macros for Automotive : 160MHz Random Access for Code and Endurance Over 10M Cycles for Data

Tomoya Ogawa,  Takashi Kono,  Takashi Ito,  Tamaki Tsuruda,  Takayuki Nishiyama,  Tsutomu Nagasawa,  Yoshiyuki Kawashima,  Hideto Hidaka,  Tadaaki Yamauchi,  

[Date]2013/4/4
[Paper #]ICD2013-13
Unified Solid-State-Storage Architecture with NAND Flash Memory and ReRAM that Tolerates 32x Higher BER for Big-Data Applications

Shuhei TANAKAMARU,  Masafumi DOI,  Ken TAKEUCHI,  

[Date]2013/4/4
[Paper #]ICD2013-14
A High Performance Storage Class Memory/MLC NAND Hybrid SSD with Anti-Fragmentation Algorithm

Kousuke Miyaji,  Hiroki Fujii,  Koh Johguchi,  Kazuhide Higuchi,  Chao Sun,  Ken Takeuchi,  

[Date]2013/4/4
[Paper #]ICD2013-15
Design of V_(3 V), V_(20V) Generator System for 3D-ReRAM and NAND Flash Memory Hybrid Solid-State Drives

Teruyoshi HATANAKA,  Koh JOHGUCHI,  Shogo HACHIYA,  Ken TAKEUCHI,  

[Date]2013/4/4
[Paper #]ICD2013-16
An Integrated Variable Positive/Negative Temperature Coefficient Read Reference Generator for MLC PCM/NAND Hybrid 3D SSD

Kousuke Miyaji,  Koh Johguchi,  Kazuhide Higuchi,  Ken Takeuchi,  

[Date]2013/4/4
[Paper #]ICD2013-17
A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs

Atsushi KAWASUMI,  Yasuhisa TAKEYAMA,  Osamu HIRABAYASHI,  Keiichi KUSHIDA,  Fumihiko TACHIBANA,  Yusuke NIKI,  Sinichi SASAKI,  Tomoaki YABE,  

[Date]2013/4/4
[Paper #]ICD2013-18
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