IEICE Technical Committee

Information and Systems-Reconfigurable Systems(Date:2015/12/01)

Presentation

Implementation of Precision Resistance Measurement of TSVs Using Analog Boundary Scan

Senling Wang(Ehime Univ.), Keisuke Kagawa(Ehime Univ.), Shuichi Kameyama(Fujitsu), Yoshinobu Higami(Ehime Univ.), Hiroshi Takahashi(Ehime Univ.),

[Date]2015-12-03
[Paper #]VLD2015-65,DC2015-61

On Correction of Temperature Influence to Delay Measurement in FPGAs

Takeru Kina(KIT), Yousuke Miyake(KIT), Yasuo Sato(KIT), Seiji Kajihara(KIT),

[Date]2015-12-03
[Paper #]VLD2015-63,DC2015-59

Fast and Accurate Estimation of Execution Cycles for ARM Architecture

Go Sato(Nagoya Univ), Yuki Ando(Nagoya Univ), Hiroaki Takada(Nagoya Univ), Shinya Honda(Nagoya Univ), Yutaka Matsubara(Nagoya Univ),

[Date]2015-12-03
[Paper #]VLD2015-73,DC2015-69

A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems

Kohta Itani(Hiroshima City Univ.), Tsuyoshi Iwagaki(Hiroshima City Univ.), Hideyuki Ichihara(Hiroshima City Univ.), Tomoo Inoue(Hiroshima City Univ.),

[Date]2015-12-03
[Paper #]VLD2015-60,DC2015-56

An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components

Junghoon Oh(JAIST), Mineo Kaneko(JAIST),

[Date]2015-12-03
[Paper #]VLD2015-62,DC2015-58

Construction and Evaluation of Three-Dimensional Heat Transfer Simulator for LSI Packages

Shougo Watanabe(Ritsumeikan Univ.), Takashi Omura(Ritsumeikan Univ.), Yuki Kitagawa(Ritsumeikan Univ.), Lei Lin(Ritsumeikan Univ.), Lin Meng(Ritsumeikan Univ.), Masahiro Fukui(Ritsumeikan Univ.),

[Date]2015-12-03
[Paper #]VLD2015-64,DC2015-60

Logic Design of A Single-Flux-Quantum Microprocessor

Koki Ishida(Kyushu Univ.), Tomonori Tsuhata(Kyushu Univ.), Masamitsu Tanaka(Nagoya Univ.), Takatsugu Ono(Kyushu Univ.), Koji Inoue(Kyushu Univ.),

[Date]2015-12-03
[Paper #]CPSY2015-73

Architecture of Bottom-up Feature Construction for Robust Computer-Aided Diagnosis System

Koki Sugi(Hiroshima Univ.), Tetsushi Koide(Hiroshima Univ.), Tatsuya Shimizu(Hiroshima Univ.), Takumi Okamoto(Hiroshima Univ.), Anh-Tuan Hoang(Hiroshima Univ.), Hikaru Sato(Hiroshima Univ.), Toru Tamaki(Hiroshima Univ.), Bisser Raytchev(Hiroshima Univ.), Kazufumi Kaneda(Hiroshima Univ.), Shigeto Toshida(Hiroshima General Hospital), Hiroshi Mieno(Hiroshima General Hospital), Shinji Tanaka(Hiroshima Univ.),

[Date]2015-12-03
[Paper #]RECONF2015-56

Suitable Feature Extraction Architecture for Real-time Computer Aided Diagnosis System on Gastrointestinal Tract

Tatsuya Shimizu(Hiroshima Univ.), Tetsushi Koide(Hiroshima Univ.), Anh-Tuan Hoang(Hiroshima Univ.), Koki Sugi(Hiroshima Univ.), Takumi Okamoto(Hiroshima Univ.), Hikaru Sato(Hiroshima Univ.), Toru Tamaki(Hiroshima Univ.), Bisser Raytchev(Hiroshima Univ.), Kazuhumi Kaneda(Hiroshima Univ.), Shigeto Yoshida(Hiroshima General Hospital), Hiroshi Mieno(Hiroshima General Hospital), Shinji Tanaka(Hiroshima Univ.),

[Date]2015-12-03
[Paper #]RECONF2015-57

Easily-testable Carry Select Adder with Online Error Detection Capability

Nobutaka Kito(Chukyo Univ.),

[Date]2015-12-03
[Paper #]VLD2015-72,DC2015-68

Accuracy Analysis of Machine Learning based Performance Modeling for Microprocessors

Yoshihiro Tanaka(Kyushu Univ.), Takatsugu Ono(Kyushu Univ.), Koji Inoue(Kyushu Univ.),

[Date]2015-12-03
[Paper #]CPSY2015-74

A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories

Masashi Tawada(Waseda Univ.), Shinji Kimura(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2015-12-03
[Paper #]VLD2015-76,DC2015-72

A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA

Kazushi Kawamura(Waseda Univ.), Masao Yanagisawa(Waseda Univ.), Nozomu Togawa(Waseda Univ.),

[Date]2015-12-03
[Paper #]VLD2015-66,DC2015-62

A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II

Yusuke Hatori(Keio Univ.), Kohei Osawa(Keio Univ.), Keigo Mizotani(Nintendo), Hiroyuki Chishiro(Keio Univ.), Nobuyuki Yamasaki(Keio Univ.),

[Date]2015-12-03
[Paper #]CPSY2015-75

[Invited Talk] Development of Via Structures in IC Package Substrates for Impedance Reduction

Tomoyuki Akaboshi(Fujitsu Lab.), Taiga Fukumori(Fujitsu Lab.), Daisuke Mizutani(Fujitsu Lab.), Motoaki Tani(Fujitsu Lab.),

[Date]2015-12-03
[Paper #]CPM2015-136,ICD2015-61

[Invited Talk] A New Concept of Memory-Logic Conjugated System and It's Spreading

Kanji Otsuka(Meisei Univ.), Youichi Sato(Meisei Univ.), Jun-ichi Kasai(MIRAI),

[Date]2015-12-03
[Paper #]CPM2015-137,ICD2015-62