| Presentation | 2015-12-03 [Invited Talk] Development of Via Structures in IC Package Substrates for Impedance Reduction Tomoyuki Akaboshi, Taiga Fukumori, Daisuke Mizutani, Motoaki Tani, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes the impedance reduction technologies in build-up package substrates for high performance CPU, such as enterprise servers or super computers. The layer connection structures of the power supply path were improved by changing a via formation in build-up substrate. As a result, we have found a via structure that improves the electrical characteristics while also yielding good connectivity and productivity. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Build-up substrate / Via structure / Impedance / Power Integrity / Reliability test |
| Paper # | CPM2015-136,ICD2015-61 |
| Date of Issue | 2015-11-24 (CPM, ICD) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
|---|---|
| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] Development of Via Structures in IC Package Substrates for Impedance Reduction |
| Sub Title (in English) | |
| Keyword(1) | Build-up substrate |
| Keyword(2) | Via structure |
| Keyword(3) | Impedance |
| Keyword(4) | Power Integrity |
| Keyword(5) | Reliability test |
| 1st Author's Name | Tomoyuki Akaboshi |
| 1st Author's Affiliation | FUJITSU LABORATORIES LTD.(Fujitsu Lab.) |
| 2nd Author's Name | Taiga Fukumori |
| 2nd Author's Affiliation | FUJITSU LABORATORIES LTD.(Fujitsu Lab.) |
| 3rd Author's Name | Daisuke Mizutani |
| 3rd Author's Affiliation | FUJITSU LABORATORIES LTD.(Fujitsu Lab.) |
| 4th Author's Name | Motoaki Tani |
| 4th Author's Affiliation | FUJITSU LABORATORIES LTD.(Fujitsu Lab.) |
| Date | 2015-12-03 |
| Paper # | CPM2015-136,ICD2015-61 |
| Volume (vol) | vol.115 |
| Number (no) | CPM-340,ICD-341 |
| Page | pp.pp.51-54(CPM), pp.51-54(ICD), |
| #Pages | 4 |
| Date of Issue | 2015-11-24 (CPM, ICD) |