| Presentation | 2015-12-03 A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II Yusuke Hatori, Kohei Osawa, Keigo Mizotani, Hiroyuki Chishiro, Nobuyuki Yamasaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recent embedded real-time systems have required multiprocessors to achieve not only real-time con-straints but also high throughput. In addition, the speed up of task by parallel and distributed processing is animportant problem. In our previous work, we proposed Responsive Task, which is a low latency real-time task onDependable Responsive Multithreaded Processor I (D-RMTP I). Responsive Task is a high-priority hard real-timetask to occupy one logical core with the interrupt wake-up structure on D-RMTP I and can be executed with dozensof μs periods. However, Responsive Task does not support parallel and distributed processing. In this paper, wepropose Parallel Responsive Task, which supports parallel and distributed processing with Responsive Task on De-pendable Responsive Multithreaded Processor II (D-RMTP II). We evaluate the latency between the release andarrival time of Parallel Responsive Task when Parallel Responsive Task is executed on one core and two cores inD-RMTP II, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded Real-Time Systems / Multiprocessor / Simultaneous Multithreading / Real-Time OS |
| Paper # | CPSY2015-75 |
| Date of Issue | 2015-11-24 (CPSY) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II |
| Sub Title (in English) | |
| Keyword(1) | Embedded Real-Time Systems |
| Keyword(2) | Multiprocessor |
| Keyword(3) | Simultaneous Multithreading |
| Keyword(4) | Real-Time OS |
| 1st Author's Name | Yusuke Hatori |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Kohei Osawa |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| 3rd Author's Name | Keigo Mizotani |
| 3rd Author's Affiliation | Nintendo Co., Ltd.(Nintendo) |
| 4th Author's Name | Hiroyuki Chishiro |
| 4th Author's Affiliation | Keio University(Keio Univ.) |
| 5th Author's Name | Nobuyuki Yamasaki |
| 5th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2015-12-03 |
| Paper # | CPSY2015-75 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-342 |
| Page | pp.pp.81-86(CPSY), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (CPSY) |