IEICE Technical Committee

Electronics-Integrated Circuits and Devices(Date:2008/07/10)

Presentation

Fabrication of Ultra Shallow Junction and Improvement of Metal Gate High-k CMOS Performance by FSP-FLA (Flexibly-Shaped-Pulse Flash-Lamp-Annealing) Technology

Takashi ONIZAWA, Shinichi KATO, Takayuki AOYAMA, Yasuo NARA, Yuzuru OHJI,

[Date]2008/7/10
[Paper #]SDM2008-146,ICD2008-56

Impact of Tantalum Composition in TaC_x/HfSiON Gate Stack on Device Performance of Aggressively Scaled CMOS Devices with SMT and Strained CESL

M. Goto, K. Tatsumura, S. Kawanaka, K. Nakajima, R. Ichihara, Y. Yoshimizu, H. Onoda, K. Nagatomo, T. Sasaki, T. Fukushima, A. Nomachi, S. Inumiya, T. Aoyama, M. Koyama, Y. Toyoshima,

[Date]2008/7/10
[Paper #]SDM2008-147,ICD2008-57

High Performance Sub-35nm Bulk CMOS with Hybrid Gate Structures of NMOS: Dopant Confinement Layer (DCL)/PMOS: Ni-FUSI by using Flash Lamp Anneal (FLA) in Ni-silicidation : Hybrid Gate Structures

H. Ohta, K. Kawamura, H. Fukutome, M. Tajima, K. Okabe, K. Ikeda, K. Hosaka, Y. Momiyama, S. Satoh, T. Sugii,

[Date]2008/7/10
[Paper #]SDM2008-148,ICD2008-58

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[Date]2008/7/10
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Notice for photocopying

[Date]2008/7/10
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奥付

[Date]2008/7/10
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