| Presentation | 2008-07-18 Fabrication of Ultra Shallow Junction and Improvement of Metal Gate High-k CMOS Performance by FSP-FLA (Flexibly-Shaped-Pulse Flash-Lamp-Annealing) Technology Takashi ONIZAWA, Shinichi KATO, Takayuki AOYAMA, Yasuo NARA, Yuzuru OHJI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose the suitable milli-second annealing (MSA) for metal/High-k device performance and ultra-shallow-junction (USJ) fabrication: flexibly-shaped-pulse flash lamp annealing (FSP-FLA). The conventional FLA treatment on metal/High-k device degrades its effective electron mobility (μeff) and bias temperature instability (BTI) characteristics. A recovery annealing treatment after FLA is most effective to recover those degradations. However, the annealing after dopant activation causes deactivation and diffusion. The FSP-FLA allowed us sub-10-milli-second annealing after activation FLA; it realizes high BTI reliability and high μeff without deactivation and diffusion. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FLA / USJ / Metal / High-k |
| Paper # | SDM2008-146,ICD2008-56 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2008/7/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fabrication of Ultra Shallow Junction and Improvement of Metal Gate High-k CMOS Performance by FSP-FLA (Flexibly-Shaped-Pulse Flash-Lamp-Annealing) Technology |
| Sub Title (in English) | |
| Keyword(1) | FLA |
| Keyword(2) | USJ |
| Keyword(3) | Metal |
| Keyword(4) | High-k |
| 1st Author's Name | Takashi ONIZAWA |
| 1st Author's Affiliation | Semiconductor Leading Edge Technologies, Inc.() |
| 2nd Author's Name | Shinichi KATO |
| 2nd Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. |
| 3rd Author's Name | Takayuki AOYAMA |
| 3rd Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. |
| 4th Author's Name | Yasuo NARA |
| 4th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. |
| 5th Author's Name | Yuzuru OHJI |
| 5th Author's Affiliation | Semiconductor Leading Edge Technologies, Inc. |
| Date | 2008-07-18 |
| Paper # | SDM2008-146,ICD2008-56 |
| Volume (vol) | vol.108 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |