| Presentation | 2008-07-18 High Performance Sub-35nm Bulk CMOS with Hybrid Gate Structures of NMOS: Dopant Confinement Layer (DCL)/PMOS: Ni-FUSI by using Flash Lamp Anneal (FLA) in Ni-silicidation : Hybrid Gate Structures H. Ohta, K. Kawamura, H. Fukutome, M. Tajima, K. Okabe, K. Ikeda, K. Hosaka, Y. Momiyama, S. Satoh, T. Sugii, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We applied Flash Lamp Annealing (FLA) in Ni-silicidation to our developed Dopant Confinement Layer (DCL) structure for the first time. DCL technique is a novel Stress Memorization Technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni Fully-silicide (Ni-FUSI) was selectively formed on gates, and both effective work function (WF) control and thinner T_ |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SiGe / SMT / DCL / High Performance CMOS / FUSI / FLA |
| Paper # | SDM2008-148,ICD2008-58 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2008/7/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Performance Sub-35nm Bulk CMOS with Hybrid Gate Structures of NMOS: Dopant Confinement Layer (DCL)/PMOS: Ni-FUSI by using Flash Lamp Anneal (FLA) in Ni-silicidation : Hybrid Gate Structures |
| Sub Title (in English) | |
| Keyword(1) | SiGe |
| Keyword(2) | SMT |
| Keyword(3) | DCL |
| Keyword(4) | High Performance CMOS |
| Keyword(5) | FUSI |
| Keyword(6) | FLA |
| 1st Author's Name | H. Ohta |
| 1st Author's Affiliation | Fujitsu Laboratories Ltd() |
| 2nd Author's Name | K. Kawamura |
| 2nd Author's Affiliation | Fujitsu Microelectronics Limited. |
| 3rd Author's Name | H. Fukutome |
| 3rd Author's Affiliation | Fujitsu Laboratories Ltd |
| 4th Author's Name | M. Tajima |
| 4th Author's Affiliation | Fujitsu Microelectronics Limited. |
| 5th Author's Name | K. Okabe |
| 5th Author's Affiliation | Fujitsu Microelectronics Limited. |
| 6th Author's Name | K. Ikeda |
| 6th Author's Affiliation | Fujitsu Laboratories Ltd |
| 7th Author's Name | K. Hosaka |
| 7th Author's Affiliation | Fujitsu Laboratories Ltd |
| 8th Author's Name | Y. Momiyama |
| 8th Author's Affiliation | Fujitsu Laboratories Ltd |
| 9th Author's Name | S. Satoh |
| 9th Author's Affiliation | Fujitsu Laboratories Ltd |
| 10th Author's Name | T. Sugii |
| 10th Author's Affiliation | Fujitsu Laboratories Ltd |
| Date | 2008-07-18 |
| Paper # | SDM2008-148,ICD2008-58 |
| Volume (vol) | vol.108 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |