10-9 : Implementation of Neuron

DATE: Thursday, October 10, 2002, 13:50 - 15:40
ROOM: 10


N10-9-1
Hardware Implementation of a Single Electron Neural Network
  Hisanao AKIMA (Laboratory for Electronic Intelligent Systems, Graduate School of Information Sciences, Tohoku University)
Saiboku YAMADA (Laboratory for Electronic Intelligent Systems, Graduate School of Information Sciences, Tohoku University)
Shigeo SATO (Laboratory for Electronic Intelligent Systems, Research Institute of Electronical Communication, Tohoku University)
Koji NAKAJIMA (Laboratory for Electronic Intelligent Systems, Research Institute of Electronical Communication, Tohoku University)

N10-9-2
Implementation of a New Stochastic Neurochip and a Study on Transitions between Limit Cycles by Stochastic Noise
  Shunsuke AKIMOTO (Laboratory for Electronic Intelligent Systems, Graduate School of Information Sciences, Tohoku University)
Ken NEMOTO (Laboratory for Electronic Intelligent Systems, Graduate School of Information Sciences, Tohoku University)
Yoshihiro HAYAKAWA (Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University)
Shigeo SATO (Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University)
Koji NAKAJIMA (Laboratory for Electronic Intelligent Systems, Research Institute of Electrical Communication, Tohoku University)

N10-9-3
An IC Implementation of the Asynchronous Pulse Neuron Model
  Takuya TANIGUCHI (Tokyo Denki University)
Yoshihiko HORIO (Tokyo Denki University)
Kazuyuki AIHARA (The University of Tokyo)

N10-9-4
Effects of Backpropagation Characteristics in a Hardware Active Dendrite Model
  Zongyang XUE (Graduate School of Science & Technology, Nihon University)
Haruki NAGAMI (Graduate School of Science & Technology, Nihon University)
Kazutaka SOMEYA (Someya Electronics Co., Ltd.)
Katsutoshi SAEKI (College of Science & Technology, Nihon University)
Yoshifumi SEKINE (College of Science & Technology, Nihon University)

N10-9-5
FPGA Based Implemetation of Hysteresis Neural Network
  Ryota AOKI (Sophia Univ,. Tokyo, Japan)
Toshiya NAKAGUCHI (Sophia Univ,. Tokyo, Japan)
Tsuyoshi OTAKE (Sophia Univ,. Tokyo, Japan)
Mamoru TANAKA (Sophia Univ,. Tokyo, Japan)

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