Engineering Sciences/NOLTA-VLSI Design Technologies(Date:2011/02/23)

Presentation
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[Date]2011/2/23
[Paper #]
目次

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[Date]2011/2/23
[Paper #]
目次

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[Date]2011/2/23
[Paper #]
Note

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[Date]2011/2/23
[Paper #]
An Architecture Exploration Method based on a Branch-and-Bound Strategy for Embedded VLIW Processors

Kohei AOKI,  Ittetsu TANIGUCHI,  Hiroyuki TOMIYAMA,  Masahiro FUKUI,  

[Date]2011/2/23
[Paper #]VLD2010-116
Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions

Mitsuya UCHIDA,  Ittestu TANIGUCHI,  Hiroyuki TOMIYAMA,  Masahiro FUKUI,  

[Date]2011/2/23
[Paper #]VLD2010-117
Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems

Masashi TAWADA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  Nozomu TOGAWA,  

[Date]2011/2/23
[Paper #]VLD2010-118
Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework

Hirotaka KAWASHIMA,  Gang ZENG,  Noritoshi ATSUMI,  Tomohiro TATEMATSU,  Hiroaki TAKADA,  

[Date]2011/2/23
[Paper #]VLD2010-119
An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization

Yoshinori SHIMADA,  Youhua SHI,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]2011/2/23
[Paper #]VLD2010-120
Investigation and Evaluation of Sleep Signal Control based on a History Information for Fine-grain Power Gating

Tetsuya MUTO,  Kimiyoshi USAMI,  

[Date]2011/2/23
[Paper #]VLD2010-121
Low Power Design of Digital Circuits using Quasi-complementary MOS Gates

Shuichi SOWA,  Mineo KANEKO,  

[Date]2011/2/23
[Paper #]VLD2010-122
Reusable Constraints of Nano-watt BGR Circuits in CMOS Process Migration

Gong CHEN,  DeLong YIN,  Bo YANG,  Dong QING,  Li JING,  Shigetoshi NAKATAKE,  

[Date]2011/2/23
[Paper #]VLD2010-123
Understanding CMOS Variability for More Moore

HIDETOSHI ONODERA,  

[Date]2011/2/23
[Paper #]VLD2010-124
Semi-static TSPC DFF Using Split-output Latch

Tomoyuki NAKABAYASHI,  Takahiro SASAKI,  Kazuhiko OHNO,  Toshio KONDO,  

[Date]2011/2/23
[Paper #]VLD2010-125
Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique

Katsuhiko IWAI,  Kenji KOJIMA,  Mitsuru SHIOZAKI,  Syunsuke ASAGAWA,  Takeshi FUJINO,  

[Date]2011/2/23
[Paper #]VLD2010-126
Evaluation of Delay-Time Difference Distribution for the Delay-Time Difference Measurable Arbiter-PUF

Takahiko MURAYAMA,  Mitsuru SHIOZAKI,  Kota FURUHASHI,  Akitaka FUKUSHIMA,  Takeshi FUJINO,  

[Date]2011/2/23
[Paper #]VLD2010-127
A Low-power Hardware Architecture for Parallel Group Signature Computation

Sumio MORIOKA,  Jun FURUKAWA,  Kazue SAKO,  

[Date]2011/2/23
[Paper #]VLD2010-128
A scalable hardware architecture for real time image recognition

Takashi AOKI,  Eiichi HOSOYA,  Takuya OTSUKA,  Akira ONOZAWA,  

[Date]2011/2/23
[Paper #]VLD2010-129
A Circuit Synthesis for High Speed Memory Access in System LSI

Kazuya KISHIDA,  Takashi KAMBE,  

[Date]2011/2/23
[Paper #]VLD2010-130
A Circuit Synthesis for Dynamic Reconfigurable Processor

Nobuyuki Araki,  Takashi KAMBE,  

[Date]2011/2/23
[Paper #]VLD2010-131
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