Presentation 2011-03-03
A scalable hardware architecture for real time image recognition
Takashi AOKI, Eiichi HOSOYA, Takuya OTSUKA, Akira ONOZAWA,
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Abstract(in English) A scalable hardware architecture is proposed for real time image recognition application. The hardware creates feature values of the input images based on HOG algorithm, which are accepted by RealAdaBoost algorithm in the following recognition phase. It achieves not only high throughput and low latency but can adjust itself flexibly to user requirements such as resolution of input images, recognition accuracy, and so on, by an efficient implementation of the weak classifiers. We have implemented the hardware on FPGAs and verified its performance.
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Keyword(in English) real time image processing / image recognition / HOG / Ada Boost / FPGA
Paper # VLD2010-129
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Conference Information
Committee VLD
Conference Date 2011/2/23(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A scalable hardware architecture for real time image recognition
Sub Title (in English)
Keyword(1) real time image processing
Keyword(2) image recognition
Keyword(3) HOG
Keyword(4) Ada Boost
Keyword(5) FPGA
1st Author's Name Takashi AOKI
1st Author's Affiliation NTT Microsystem Integration Laboratories()
2nd Author's Name Eiichi HOSOYA
2nd Author's Affiliation NTT Microsystem Integration Laboratories
3rd Author's Name Takuya OTSUKA
3rd Author's Affiliation NTT Microsystem Integration Laboratories
4th Author's Name Akira ONOZAWA
4th Author's Affiliation NTT Microsystem Integration Laboratories
Date 2011-03-03
Paper # VLD2010-129
Volume (vol) vol.110
Number (no) 432
Page pp.pp.-
#Pages 6
Date of Issue