Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1997/03/06)

Presentation
表紙

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[Date]1997/3/6
[Paper #]
目次

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[Date]1997/3/6
[Paper #]
C-Testable Design of Multipliers Based on the Modified Booth Algorithm

Kwame Osei Boateng,  Hiroshi Takahashi,  Yuzo Takamatsu,  

[Date]1997/3/6
[Paper #]VLD96-87,ICD96-197
Design of Parallel Multipliers using Neuron MOS Multiple Input Adders

Kei HIROSE,  Hiroto YASUURA,  

[Date]1997/3/6
[Paper #]VLD96-88,ICD96-198
Memorypath Design for PPRAM-type Merged DRAM/Logic LSI

Hiroto TOMITA,  Kazuaki MURAKAMI,  

[Date]1997/3/6
[Paper #]VLD96-89,ICD96-199
On Bottom-up Algorithms for Bi-decomposition of Logic Functions

Yusuke Matsunaga,  

[Date]1997/3/6
[Paper #]VLD96-90,ICD96-200
A Reduction Method of Register Transfer Level Logic Circuits for Design Verification

Takanori Sakate,  Shinji Kimura,  Katsumasa Watanabe,  

[Date]1997/3/6
[Paper #]VLD96-91,ICD96-201
Sum-Difference Based On-line Error Correcting Scheme for Global Fault Tolerance with Local Error Correction

Yasufumi Tsumagari,  Mineo Kaneko,  

[Date]1997/3/6
[Paper #]VLD96-92,ICD96-202
A Hypergraph Partitioning Algorithm Considering Path-Cut Constraints for Circuit Partitioning

Shin'ichi HIRATANI,  Shin'ichi WAKABAYASI,  Tetsushi KOIDE,  

[Date]1997/3/6
[Paper #]VLD96-93,ICD96-203
Towards System on Silicon Era : Goal of VSI Alliance

Kenji YOSHIDA,  

[Date]1997/3/6
[Paper #]VLD96-94,ICD96-204
Panel Discussion : What kinds of CAD tools have to be developed for System-on-Silicon era?

Hiroto Yasuura,  Eiji Masuda,  Takashi Hotta,  Michiaki Muraoka,  Yusuke Matsunaga,  Nobuto Ono,  

[Date]1997/3/6
[Paper #]VLD96-95,ICD96-205
[OTHERS]

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[Date]1997/3/6
[Paper #]