| Presentation | 1997/3/6 Memorypath Design for PPRAM-type Merged DRAM/Logic LSI Hiroto TOMITA, Kazuaki MURAKAMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Merged DRAM/logic chip architectures, such as PPRAM(Parallel Proccssing RAM), will improve the design freedom as compared with conventional computer systems consisting of separate MPU and DRAM chips. For example, they will allow us to exploit at least three on-chip memorypath architectures: (a)register-register architecture with cache memory, (b)register-register architecture without cache memory, and (c)memory-memory architecture. Regarding the real LSI design, it is necessary to tradeoff between (1)performance, (2)areas, and (3)power. This paper develops the models of the memorypaths for the register-register architecture with cache memory and their area formulas, in order to enable the comparison of the memorypath designs. Then, the paper evaluates the area characteristics of these memorypath models quantitatively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | PPRAM / merged DRAM/logic LSI / DRAM / circuit design |
| Paper # | VLD96-89,ICD96-199 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1997/3/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Memorypath Design for PPRAM-type Merged DRAM/Logic LSI |
| Sub Title (in English) | |
| Keyword(1) | PPRAM |
| Keyword(2) | merged DRAM/logic LSI |
| Keyword(3) | DRAM |
| Keyword(4) | circuit design |
| 1st Author's Name | Hiroto TOMITA |
| 1st Author's Affiliation | Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University() |
| 2nd Author's Name | Kazuaki MURAKAMI |
| 2nd Author's Affiliation | Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University |
| Date | 1997/3/6 |
| Paper # | VLD96-89,ICD96-199 |
| Volume (vol) | vol.96 |
| Number (no) | 555 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |