Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1995/07/21)

Presentation
表紙

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[Date]1995/7/21
[Paper #]
目次

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[Date]1995/7/21
[Paper #]
Design Verification of Arithmetic Circuits Using Residue BDD's

Shinji Kimura,  

[Date]1995/7/21
[Paper #]
Multi-Level Logic Minimization based on Multi-Signal Implications

Masayuki Yuguchi,  Yuichi Nakamura,  Kazutoshi Wakabayashi,  Tomoyuki Fujita,  

[Date]1995/7/21
[Paper #]
A Partitioning-based Logic Optimization Method for Large Scale Circuits with Boolean Matrix

Yuichi Nakamura,  Takeshi Yoshimura,  

[Date]1995/7/21
[Paper #]
MacroPRISM : High Density Macro Layout System

Kazuyuki Kawauchi,  Jun-ichi Kikkawa,  Tsutomu Nakamori,  

[Date]1995/7/21
[Paper #]
A Compaction Algorithm which Provides Flexible Transistor Layout Model for Technology Changes

Masahiro Fukui,  Syunji Saika,  Toshiro Akino,  

[Date]1995/7/21
[Paper #]
A Bounded-Skew Clock Layout Technique Based on Circuit Partitioning

Hidenori Sato,  Akira Onozawa,  Hiroaki Matsuda,  

[Date]1995/7/21
[Paper #]
KUE-CHIP2 : A Microprocessor for Education of LSI Design and Computer Hardware

Hiroyuki Kanbara,  Hiroto Yasuura,  

[Date]1995/7/21
[Paper #]
[OTHERS]

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[Date]1995/7/21
[Paper #]