Presentation 1995/7/21
A Partitioning-based Logic Optimization Method for Large Scale Circuits with Boolean Matrix
Yuichi Nakamura, Takeshi Yoshimura,
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Abstract(in English) This paper presents a new logic partitioning method for optimizing large scale circuits. The proposed method partitions a given circuit into transitive fanin-disjoint sub-circuits by matrix operations, so that various optimization methods can be applied to each partitioned sub-circuit instead of the whole circuit. Thus, the optimization results which are obtained by the proposed partitioning and optimization for each partitioned sub-circuits, are simular to whole logic optimization. Experimental results show that the proposed method achieves high-quality design comparable to the one optimized for the whole circuits, with much shorter time (1/20). Thus, the circuits with over 10,000 gates can be optimized by the proposed partitioning.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Logic Synthesis / Logic Partitioning / Logic Optimization
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Committee VLD
Conference Date 1995/7/21(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
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Title (in English) A Partitioning-based Logic Optimization Method for Large Scale Circuits with Boolean Matrix
Sub Title (in English)
Keyword(1) Logic Synthesis
Keyword(2) Logic Partitioning
Keyword(3) Logic Optimization
1st Author's Name Yuichi Nakamura
1st Author's Affiliation C&C Research Laboratories, NEC Corporation()
2nd Author's Name Takeshi Yoshimura
2nd Author's Affiliation C&C Research Laboratories, NEC Corporation
Date 1995/7/21
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Volume (vol) vol.95
Number (no) 171
Page pp.pp.-
#Pages 7
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