Engineering Sciences/NOLTA-VLSI Design Technologies(Date:1993/12/16)

Presentation
表紙

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[Date]1993/12/16
[Paper #]
目次

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[Date]1993/12/16
[Paper #]
An Efficient Hill-Climbing Algorithm For Partitioning

Toshiyuki Shibuya,  Kaoru Kawamura,  

[Date]1993/12/16
[Paper #]VLD93-74
A parallel routing algorithm based on newral networks

Kyotaro Suzuki,  Akira Hanada,  Hideharu Amano,  Yoshiyasu Takefuji,  

[Date]1993/12/16
[Paper #]VLD93-75
Technology mapping with simulated annealing

Katsumi Harashima,  Kunio Fukunaga,  Hideo Kosako,  

[Date]1993/12/16
[Paper #]VLD93-76
A Delay Minimization technique with Partial Collapsing

Koichi Sato,  Masamichi Kawarabayashi,  Hideyuki Emura,  Naotaka Maeda,  

[Date]1993/12/16
[Paper #]VLD93-77
An MCM Routing Method for Via Minimization Considering Cross talk

Tetsuya Miyoshi,  Tetsushi Koide,  Shin'ichi Wakabayashi,  Noriyoshi Yoshida,  

[Date]1993/12/16
[Paper #]VLD93-78
On Rollbacks in Parallel Logic Simulation for Tree Connected Circuit

Tadashi Seko,  Tohru Kikuno,  

[Date]1993/12/16
[Paper #]VLD93-79
A formal verification method based on circut partitioning corsidering BDD size

Toshihiro Nakaoka,  Shin'ichi Wakabayashi,  Tetsushi Koide,  Noriyoshi Yoshida,  

[Date]1993/12/16
[Paper #]VLD93-80
An algorithm for Boolean matching utilizing structural information

Yusuke Matsunaga,  

[Date]1993/12/16
[Paper #]VLD93-81
Random Generation of Test Instances for Evaluating Logic Optimizers

Kensuke Hino,  Kazuo Iwama,  

[Date]1993/12/16
[Paper #]VLD93-82
Latch insertion method for synchronous circuits realized as LUT- based FPGAs that improves performance

Toshiaki Miyazaki,  Hiroshi Nakada,  Akihiro Tsutsui,  Kazuhisa Yamada,  Naohisa Ohta,  

[Date]1993/12/16
[Paper #]VLD93-83
EURO-DAC′93Report

Masaharu Imai,  

[Date]1993/12/16
[Paper #]VLD93-84
[OTHERS]

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[Date]1993/12/16
[Paper #]