Presentation 1993/12/16
Technology mapping with simulated annealing
Katsumi Harashima, Kunio Fukunaga, Hideo Kosako,
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Abstract(in English) In this paper,we will present a technology mapping with the improved simulated annealing.Simulated annealing methods have been used for placement circuit modules in the layout phase,can get good solutions.However,they are very slowly.Therefor,we attempt this method speed-up decreasing a temperature-parameter non- linealy,and apply this one to a technology-mapping.As a result of, our method is faster than the logic synthesis system MIS and gets good solutions.
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Keyword(in English) technology mapping / simulated annealing / logic synthesis
Paper # VLD93-76
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Committee VLD
Conference Date 1993/12/16(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Technology mapping with simulated annealing
Sub Title (in English)
Keyword(1) technology mapping
Keyword(2) simulated annealing
Keyword(3) logic synthesis
1st Author's Name Katsumi Harashima
1st Author's Affiliation College of Engineering,University of Osaka Prefecture()
2nd Author's Name Kunio Fukunaga
2nd Author's Affiliation College of Engineering,University of Osaka Prefecture
3rd Author's Name Hideo Kosako
3rd Author's Affiliation College of Engineering,University of Osaka Prefecture
Date 1993/12/16
Paper # VLD93-76
Volume (vol) vol.93
Number (no) 391
Page pp.pp.-
#Pages 6
Date of Issue