Presentation 1993/12/16
Latch insertion method for synchronous circuits realized as LUT- based FPGAs that improves performance
Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper presents a new method for improving the performance of synchronous circuits configured in look-up table based FPGAs; the initial circuit configuration is unchanged except for the addition of some latches.We formulate the problem in Integer Liner Programming(ILP)and find the latch insertion points.Because our method does not change the initial configuration,the circuit performance must be improved if the method can be applied to the circuit.After formulating the problem,the effectiveness of the method is shown by some experimental results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) retiming / ILP / digital signal transport
Paper # VLD93-83
Date of Issue

Conference Information
Committee VLD
Conference Date 1993/12/16(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Latch insertion method for synchronous circuits realized as LUT- based FPGAs that improves performance
Sub Title (in English)
Keyword(1) retiming
Keyword(2) ILP
Keyword(3) digital signal transport
1st Author's Name Toshiaki Miyazaki
1st Author's Affiliation NTT Transmission Systems Laboratories()
2nd Author's Name Hiroshi Nakada
2nd Author's Affiliation NTT Transmission Systems Laboratories
3rd Author's Name Akihiro Tsutsui
3rd Author's Affiliation NTT Transmission Systems Laboratories
4th Author's Name Kazuhisa Yamada
4th Author's Affiliation NTT Transmission Systems Laboratories
5th Author's Name Naohisa Ohta
5th Author's Affiliation NTT Transmission Systems Laboratories
Date 1993/12/16
Paper # VLD93-83
Volume (vol) vol.93
Number (no) 391
Page pp.pp.-
#Pages 7
Date of Issue