Engineering Sciences/NOLTA-Reliability(Date:2024/01/29)

Presentation
High-speed division circuits using BCD codes

Fumiya Kanai(Gunma Univ.),  Yuki Tanaka(Gunma Univ.),  

[Date]2024-01-29
[Paper #]VLD2023-89,RECONF2023-92
100GbEによるデータ収集システムの動作検証用トラフィックエミュレータの検討

Kazuya Nagasawa,  Yasunori Osana,  

[Date]2024-01-29
[Paper #]VLD2023-82,RECONF2023-85
Random number generation on the Rocket core with a built-in LFSR

Takayoshi Shikano(Toyohashi Tech.),  Shuichi Ichikawa(Toyohashi Tech.),  

[Date]2024-01-29
[Paper #]VLD2023-80,RECONF2023-83
KyokkoへのCRCによるエラー検出機能の実装

Hisayuki Tamashiro(Univ. Ryukyus),  Akinobu Tomori(Kumamoto Univ.),  Yasunori Osana(Kumamoto Univ.),  

[Date]2024-01-29
[Paper #]VLD2023-83,RECONF2023-86
Comparison of latch-based circuit and flip-flop-based circuit in actual device

Kenji Takahashi(Sony Semiconductor Solutions),  Tadaaki Tanimoto(Sony Semiconductor Solutions),  Keizo Hiraga(Sony Semiconductor Solutions),  Masayuki Hayashi(Sony Semiconductor Solutions),  Takato Inoue(Sony Semiconductor Solutions),  Kazuhiro Bessho(Sony Semiconductor Solutions),  Toshimasa Shimizu(Sony Semiconductor Solutions),  

[Date]2024-01-29
[Paper #]VLD2023-91,RECONF2023-94
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis

Tadaaki Tanimoto(Sony Semiconductor Solutions),  Keizo Hiraga(Sony Semiconductor Solutions),  Toshihiko Katou(Sony Semiconductor Solutions),  Kazuhiro Bessho(Sony Semiconductor Solutions),  Toshimasa Shimizu(Sony Semiconductor Solutions),  

[Date]2024-01-29
[Paper #]VLD2023-90,RECONF2023-93
Suppression of output bit width growth in AFE stochastic computing units

Daiki Seto(Aichi Inst. Tech.),  Naoki Fujieda(Aichi Inst. Tech.),  

[Date]2024-01-29
[Paper #]VLD2023-81,RECONF2023-84
FPGA implementation of Data (De)Compression for State Vector Quantum Simulator

Kaijie Wei(Keio Univ.),  Hideharu Amano(Keio Univ.),  Ryohei Niwase(Tsukuba Univ.),  Takefumi Miyoshi(WasaLabo),  Yoshiki Yamaguchi(Tsukuba Univ.),  

[Date]2024-01-29
[Paper #]VLD2023-87,RECONF2023-90
極低温下で動作する信号処理ASICの実現に向けたFPGA向けデザインのマイグレーション

Takashi Imagawa(Meiji Univ.),  Yuki Koyama(KIT),  Kazutoshi Kobayashi(KIT),  Takefumi Miyoshi(QuEL),  

[Date]2024-01-29
[Paper #]VLD2023-85,RECONF2023-88
[Invited Talk] Role of FPGAs in Quantum Network Architectures

Fumiaki Mizuno(Keio Univ.),  

[Date]2024-01-29
[Paper #]VLD2023-84,RECONF2023-87
A large scale quantum computer simulation using an FPGA board with directly connected SATA disks

Hideharu Amano(Keio Univ.),  Wei Kaijie(Keio Univ.),  Yoshiki Yamaguchi(Univ. of Tsukuba),  Ryohei Niwase(Univ. of Tsukuba),  Takefumi Miyoshi(Wasalab),  

[Date]2024-01-29
[Paper #]VLD2023-88,RECONF2023-91
A Study of Low Latency Feedback Operation Architecture for Superconducting Qubit

Takefumi Miyoshi(QuEL/e-trees),  Keisuke Koike(e-trees),  Kazuhisa Ogawa(Osaka Univ.),  Ryo Matsuda(Osaka Univ.),  Hidehisa Shiomi(Osaka Univ.),  Shinichi Morisaka(Osaka Univ./QuEL),  Yutaka Tabuchi(RIKEN),  Makoto Negoro(Osaka Univ.),  

[Date]2024-01-29
[Paper #]VLD2023-86,RECONF2023-89
FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection

Qingyu Zeng(Tokyo Tech),  Yuko Hara(Tokyo Tech),  

[Date]2024-01-30
[Paper #]VLD2023-97,RECONF2023-100
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems

Kei Mikami(Kansei Gakuin Univ.),  Nagisa Ishiura(Kansei Gakuin Univ.),  Hiroyuki Tomiyama(Ritsumeikan Univ.),  Hiroyuki Kanbara(ASTEM),  

[Date]2024-01-30
[Paper #]VLD2023-94,RECONF2023-97
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer

Sho Kishimoto(Kwansei Gakuin Univ.),  Nagisa Ishiukra(Kwansei Gakuin Univ.),  

[Date]2024-01-30
[Paper #]VLD2023-95,RECONF2023-98
Exploration of Acceleration of FPGA-based Linear Equation Solver using Approximate Division in Electronic Circuit Simulator

Naoki Kakine(HCU),  Shuto Yuya(HCU),  Tetsuo Hironaka(HCU),  Atsushi Kubota(HCU),  

[Date]2024-01-30
[Paper #]VLD2023-96,RECONF2023-99
Design space exploration for a CGRA architecture that efficiently handles the Systolic algorithm

Hajime Takishita(Keio Univ.),  Takuya Kojima(UTokyo),  Hideharu Amano(Keio Univ.),  

[Date]2024-01-30
[Paper #]VLD2023-92,RECONF2023-95
Comparison of Graph Data Structures for Breadth-First Search Accelerator HyGTA2

Jun Akimoto(Hiroshima City Univ),  Kazuya Tanigawa(Hiroshima City Univ),  Kentaro Sano(Processor Research Team,RIKEN Center for Computational Science),  Tetsuo Hironaka(Hiroshima City Univ),  

[Date]2024-01-30
[Paper #]VLD2023-98,RECONF2023-101
A Prototype Design of an Embedded Real-Time GPU

Takafumi Tarui(Keio Univ.),  Nobuyuki Yamasaki(Keio Univ.),  

[Date]2024-01-30
[Paper #]VLD2023-93,RECONF2023-96