| Presentation | 2024-01-30 Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer Sho Kishimoto, Nagisa Ishiukra, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this article, we present a method for implementing external memory access within the context of binary synthesis utilizing commercial high-level synthesis systems. Binary synthesis, which translates binary program codes into hardware designs, enables synthesis of hardware from programs using assembly or inline assembly. Nakamichi et al. has proposed an approach for facilitating implementation of binary synthezers, in which binary programs are once translated into C programs and then processed by a high-level synthezer. However, binary synthesizers developed so far using this method embed memory within the synthesized hardware, thereby impeding data sharing among various hardware components and memory-mapped I/O. This paper aims to enhance Nakamichi's method to enable external memory access through I/O ports of synthesized hardware, facilitating memory-mapped I/O as well. A binary synthesizer, implemented based on the proposed method, demonstrates that external memory access and memory-mapped I/O are achievable without incurring significant overhead in terms of circuit size and execution cycle count. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Binary synthesis / High-level synthesis / RISC-V / ISA / Embedded system |
| Paper # | VLD2023-95,RECONF2023-98 |
| Date of Issue | 2024-01-22 (VLD, RECONF) |
| Conference Information | |
| Committee | RECONF / VLD |
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| Conference Date | 2024/1/29(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | AIRBIC Meeting Room 1-4 |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Vice Chair | Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Yuichi Sakurai(Hitachi) |
| Secretary | Yasushi Inoguchi(NEC) / Tomonori Izumi(Toyohashi Univ. of Tech.) / Yuichi Sakurai(Socionext) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer |
| Sub Title (in English) | |
| Keyword(1) | Binary synthesis |
| Keyword(2) | High-level synthesis |
| Keyword(3) | RISC-V |
| Keyword(4) | ISA |
| Keyword(5) | Embedded system |
| 1st Author's Name | Sho Kishimoto |
| 1st Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiukra |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kwansei Gakuin Univ.) |
| Date | 2024-01-30 |
| Paper # | VLD2023-95,RECONF2023-98 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-373,RECONF-374 |
| Page | pp.pp.87-92(VLD), pp.87-92(RECONF), |
| #Pages | 6 |
| Date of Issue | 2024-01-22 (VLD, RECONF) |