| Presentation | 2024-01-30 Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path delay, within the context of full hardware implementation of RTOS-based systems. Oosako and Muguruma previously proposed methods to enhance the response performance of real-time systems by implementing both tasks/handlers and RTOS kernel functions as hardware. However, their methods assume around 8 tasks, and surpassing this count results in impractical circuit size and critical path delay. In our work, we address these scalability challenges by adopting a more efficient circuit design. This involves reducing the bit count of state registers responsible for storing task states and integrating them into a single register per task. Additionally, we control the critical path delay by multi-stage implementation of the service request arbitration circuit. We have designed a management module that incorporates RTOS functions for 64 tasks based on our proposed method. This design has led to a substantial reduction in circuit size, approximately 48%, and a decrease in critical path delay by around 55% when compared to the previous design. Furthermore, we have observed an average reduction of approximately 1 cycle in the number of execution cycles from the initiation of a task requesting service processing to receiving the return value. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Real-Time Systems / RTOS / System Synthesis / Hardware Accelerator / TOPPERS/ASP3 / High-Level Synthesis |
| Paper # | VLD2023-94,RECONF2023-97 |
| Date of Issue | 2024-01-22 (VLD, RECONF) |
| Conference Information | |
| Committee | RECONF / VLD |
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| Conference Date | 2024/1/29(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | AIRBIC Meeting Room 1-4 |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Chair | Yoshiki Yamaguchi(Tsukuba Univ.) / Shigetoshi Nakatake(Univ. of Kitakyushu) |
| Vice Chair | Yasushi Inoguchi(JAIST) / Tomonori Izumi(Ritsumeikan Univ.) / Yuichi Sakurai(Hitachi) |
| Secretary | Yasushi Inoguchi(NEC) / Tomonori Izumi(Toyohashi Univ. of Tech.) / Yuichi Sakurai(Socionext) |
| Assistant | Yukitaka Takemura(INTEL) / Yasunori Osana(Kumamoto Univ.) / Takuma Nishimoto(Hitachi) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems |
| Sub Title (in English) | |
| Keyword(1) | Real-Time Systems |
| Keyword(2) | RTOS |
| Keyword(3) | System Synthesis |
| Keyword(4) | Hardware Accelerator |
| Keyword(5) | TOPPERS/ASP3 |
| Keyword(6) | High-Level Synthesis |
| 1st Author's Name | Kei Mikami |
| 1st Author's Affiliation | Kwansei Gakuin University(Kansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University(Kansei Gakuin Univ.) |
| 3rd Author's Name | Hiroyuki Tomiyama |
| 3rd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 4th Author's Name | Hiroyuki Kanbara |
| 4th Author's Affiliation | Advanced Science, Technology & Management Research Institute of KYOTO(ASTEM) |
| Date | 2024-01-30 |
| Paper # | VLD2023-94,RECONF2023-97 |
| Volume (vol) | vol.123 |
| Number (no) | VLD-373,RECONF-374 |
| Page | pp.pp.81-86(VLD), pp.81-86(RECONF), |
| #Pages | 6 |
| Date of Issue | 2024-01-22 (VLD, RECONF) |