IEICE Technical Committee

Electronics-Integrated Circuits and Devices(Date:2010/04/15)

Presentation

[Date]2010/4/15
[Paper #]

A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm^2 Cell in 32nm High-k Metal Gate CMOS

Yuki FUJIMURA, Osamu HIRABAYASHI, Takahiko SASAKI, Azuma SUZUKI, Atsushi KAWASUMI, Yasuhisa TAKEYAMA, Keiichi KUSHIDA, Gou FUKANO, Akira KATAYAMA, Yusuke NIKI, Tomoaki YABE,

[Date]2010/4/15
[Paper #]ICD2010-1

Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies : A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias

Koji NII, Makoto YABUUCHI, Yasumasa TSUKAMOTO, Yuuichi HIRANO, Toshiaki IWAMATSU, Yuji KIHARA,

[Date]2010/4/15
[Paper #]ICD2010-2

A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist

Makoto YABUUCHI, Koji NII, Yasumasa TSUKAMOTO, Yasunobu NAKASE, Hirofumi SHINOHARA,

[Date]2010/4/15
[Paper #]ICD2010-3

A 40nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation

Shigenobu KOMATSU, Masanao YAMAOKA, Masao MORIMOTO, Noriaki MAEDA, Yasuhisa SHIMAZAKI, Kenichi OSADA,

[Date]2010/4/15
[Paper #]ICD2010-4

32% Lower Active Power, 42% Lower Leakage Current Ferroelectric 6T-SRAM with V_	Self-Adjusting Function for 60% Larger Static Noise Margin (SNM)

Shuhei TANAKAMARU, Teruyoshi HATANAKA, Ryoji YAJIMA, Mitsue TAKAHASHI, Shigeki SAKAI, Ken TAKEUCHI,

[Date]2010/4/15
[Paper #]ICD2010-5

Low-V_T CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays

Akira KOTABE, Yoshimitsu YANAGAWA, Satoru AKIYAMA, Tomonori SEKIGUCHI,

[Date]2010/4/15
[Paper #]ICD2010-6

A 64Mbit MRAM with Clamped-Reference and Adequate-Reference Schemes

K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, Asao Y. /, T. Kajiyama, M. Iwayma, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, Y. Watanabe,

[Date]2010/4/15
[Paper #]ICD2010-7

Overview of Chain FeRAM Technology and Scalable Shield-Bitline-Overdrive Technique

Daisaburo TAKASHIMA, Hidehiro SHIGA, Daisuke HASHIMOTO, Tadashi MIYAKAWA, Tohru OZAKI, Hiroyuki KANAYA, Susumu SHUTO, Koji YAMAKAWA, Iwao KUNISHIMA,

[Date]2010/4/15
[Paper #]ICD2010-8

Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array

Daisuke SUZUKI, Masanori NATSUI, Shoji IKEDA, Haruhiro HASEGAWA, Katsuya MIURA, Jun HAYAKAWA, Tetsuo ENDOH, Hideo OHNO, Takahiro HANYU,

[Date]2010/4/15
[Paper #]ICD2010-9

A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout

Riichiro TAKEMURA, Takayuki KAWAHARA, Katsuya MIURA, Hiroyuki YAMAMOTO, Jun HAYAKAWA, Nozomu MATSUZAKI, Kazuo ONO, Michihiko YAMANOUCHI, Kenchi ITO, Hiromasa TAKAHASHI, Shoji IKEDA, Haruhiro HASEGAWA, Hideyuki MATSUOKA, Hideo OHNO,

[Date]2010/4/15
[Paper #]ICD2010-10

Ferroelectric (Fe)-NAND Flash Memory with Non-volatile Page Buffer for Data Center Application Enterprise Solid-State Drives (SSD)

Teruyoshi HATANAKA, Ryoji YAJIMA, Takeshi HORIUCHI, Shouyu Wang, Xizhen Zhang, Mitsue TAKAHASHI, Shigeki SAKAI, Ken TAKEUCHI,

[Date]2010/4/15
[Paper #]ICD2010-11

Multi-stacked 1G cell/layer Pipe-shaped BiCS Flash Memory

[Date]2010/4/15
[Paper #]ICD2010-12

Design Technology of stacked NAND FeRAM

Koichi Sugano, Shigeyoshi Watanabe,

[Date]2010/4/15
[Paper #]ICD2010-13

Study of stacked NOR type MRAM

Shouto TAMAI, Shigeyoshi WATANABE,

[Date]2010/4/15
[Paper #]ICD2010-14