| Presentation | 2010-04-22 Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array Daisuke SUZUKI, Masanori NATSUI, Shoji IKEDA, Haruhiro HASEGAWA, Katsuya MIURA, Jun HAYAKAWA, Tetsuo ENDOH, Hideo OHNO, Takahiro HANYU, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnetic Tunnel Junction) device-based logic technology. To utilize a capability of MTJ devices, the combinational logic circuitry is implemented based on differential current-mode logic methodology. Since the circuit performs current-mode logic operations under low voltage swing, the variation of current flows through MTJ devices can be applied as logic signals directly with no signal amplification. It results in a compact circuit implementation. The proposed LUT circuit fabricated by a 0.14μm CMOS/MTJ-hybrid process achieves area reduction by 2/3 compared to a conventional SRAM-based one, and complete elimination of standby power dissipation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MTJ device / FPGA / LUT / Logic-in-memory circuit / Current-mode-logic |
| Paper # | ICD2010-9 |
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| Committee | ICD |
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| Conference Date | 2010/4/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array |
| Sub Title (in English) | |
| Keyword(1) | MTJ device |
| Keyword(2) | FPGA |
| Keyword(3) | LUT |
| Keyword(4) | Logic-in-memory circuit |
| Keyword(5) | Current-mode-logic |
| 1st Author's Name | Daisuke SUZUKI |
| 1st Author's Affiliation | Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku Univ.() |
| 2nd Author's Name | Masanori NATSUI |
| 2nd Author's Affiliation | Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku Univ. |
| 3rd Author's Name | Shoji IKEDA |
| 3rd Author's Affiliation | Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku Univ. |
| 4th Author's Name | Haruhiro HASEGAWA |
| 4th Author's Affiliation | Hitachi Advanced Research Laboratory |
| 5th Author's Name | Katsuya MIURA |
| 5th Author's Affiliation | Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku Univ.:Hitachi Advanced Research Laboratory |
| 6th Author's Name | Jun HAYAKAWA |
| 6th Author's Affiliation | Hitachi Advanced Research Laboratory |
| 7th Author's Name | Tetsuo ENDOH |
| 7th Author's Affiliation | Center for Interdisciplinary Research, Tohoku University |
| 8th Author's Name | Hideo OHNO |
| 8th Author's Affiliation | Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku Univ. |
| 9th Author's Name | Takahiro HANYU |
| 9th Author's Affiliation | Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku Univ. |
| Date | 2010-04-22 |
| Paper # | ICD2010-9 |
| Volume (vol) | vol.110 |
| Number (no) | 9 |
| Page | pp.pp.- |
| #Pages | 6 |
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