Electronics-Integrated Circuits and Devices(Date:1999/05/27)

Presentation
表紙

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[Date]1999/5/27
[Paper #]
目次

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[Date]1999/5/27
[Paper #]
A 1.6 GByte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme

Hiroshi Ito,  Satoru Takase,  Natsuki Kushiyama,  

[Date]1999/5/27
[Paper #]ICD99-20
A 250Mb/s/pin 1Gb Double Data Rate SDRAM

Mamoru Fujita,  Yasuhiro Takai,  Kyouichi Nagata,  Satoshi Isa,  Shigeyuki Nakazawa,  Atsunori Hirobe,  Yasuo Kobayashi,  Takashi Okuda,  

[Date]1999/5/27
[Paper #]ICD99-21
Development of 64Mb High-speed DRAM Macro

Noritsugu Nakamura,  Tohru Kimura,  Koichi Takeda,  Yoshiharu Aimoto,  Takahiro Iwasaki,  Youetsu Nakazawa,  Hideo Toyoshima,  Masayuki Hamada,  Mitsuhiro Togo,  Hajime Nobusawa,  Takaho Tanigawa,  

[Date]1999/5/27
[Paper #]ICD99-22
Access optimizer for embedded DRAMs

Seiji Miura,  Kazushige Ayukawa,  Makoto Toda,  Takao Watanabe,  Tetsuya Iwamura,  Kouichi Hoshi,  Jun Sato,  Kazumasa Yanagisawa,  

[Date]1999/5/27
[Paper #]ICD99-23
A 42.4G-Byte/sec bandwidth and av.20M-Triangle/sec rendering-rate on a 3D-Frame buffer

Kazunari Inoue,  Hideaki Abe,  Kaori Mori,  Shuji Fukagawa,  

[Date]1999/5/27
[Paper #]ICD99-24
Market and Technical Trend of Large Density, High Speed DRAMs

Yoshitomo Asakura,  

[Date]1999/5/27
[Paper #]ICD99-25
Current Issues and Directions on A system LSI with embedded DRAM

Katsumi Dosaka,  Kazutami Arimoto,  

[Date]1999/5/27
[Paper #]ICD99-26
[OTHERS]

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[Date]1999/5/27
[Paper #]