| Presentation | 1999/5/27 Access optimizer for embedded DRAMs Seiji Miura, Kazushige Ayukawa, Makoto Toda, Takao Watanabe, Tetsuya Iwamura, Kouichi Hoshi, Jun Sato, Kazumasa Yanagisawa, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Embedded DRAMs will be faced new walls in the future. The first one is the on Chip CPU-DRAM bottleneck. And the second one is the access conflict between DRAM masters. We propose an "access optimizer", an interface module for embedded DRAMs, to overcome these walls. The benchmark analysis shows that the acccess optimizer reduces the L1 cache fill latency by 30% and the chip performance with access conflict by 39%". Test chip, integrated the access optimizer and an 8Mbit DRAM macro, was fabricated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | embedded DRAMs / embedded DRAM interface module / DRAM macro / access conflict |
| Paper # | ICD99-23 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1999/5/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Access optimizer for embedded DRAMs |
| Sub Title (in English) | |
| Keyword(1) | embedded DRAMs |
| Keyword(2) | embedded DRAM interface module |
| Keyword(3) | DRAM macro |
| Keyword(4) | access conflict |
| 1st Author's Name | Seiji Miura |
| 1st Author's Affiliation | Central Research Lab., Hitachi, Ltd() |
| 2nd Author's Name | Kazushige Ayukawa |
| 2nd Author's Affiliation | Central Research Lab., Hitachi, Ltd |
| 3rd Author's Name | Makoto Toda |
| 3rd Author's Affiliation | Central Research Lab., Hitachi, Ltd |
| 4th Author's Name | Takao Watanabe |
| 4th Author's Affiliation | Central Research Lab., Hitachi, Ltd |
| 5th Author's Name | Tetsuya Iwamura |
| 5th Author's Affiliation | Hitachi ULSI Systems co. Ltd |
| 6th Author's Name | Kouichi Hoshi |
| 6th Author's Affiliation | Hitachi ULSI Systems co. Ltd |
| 7th Author's Name | Jun Sato |
| 7th Author's Affiliation | Semiconductor & Integrated Circuit Div., Hitachi, Ltd |
| 8th Author's Name | Kazumasa Yanagisawa |
| 8th Author's Affiliation | Semiconductor & Integrated Circuit Div., Hitachi, Ltd |
| Date | 1999/5/27 |
| Paper # | ICD99-23 |
| Volume (vol) | vol.99 |
| Number (no) | 93 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |