| Presentation | 1999/5/27 A 1.6 GByte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme Hiroshi Ito, Satoru Takase, Natsuki Kushiyama, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes the two circuit technologies adopted for a 1,6GByte/s 72Mb Direct RDRAM with 16 independent bank architecture. "Flexible Mapping Redundancy Technique" suits for multi-bank, multi-bit memory, because flexible relationship between spare element and fuse-set allows to reduce the number of fuse-set. This achieved 13% smaller chip size for the DRAM with 16 banks than the conventional 1-to-1 redundancy. Also, it is introduced "Additional Refresh Scheme" which use longer refresh period and add the refresh operation only for weak cells. With this scheme, the refresh current of the DRAM is reduced to about 1/4 with 0.6% area penalty. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / multi bank / redundancy / refresh |
| Paper # | ICD99-20 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1999/5/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 1.6 GByte/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | multi bank |
| Keyword(3) | redundancy |
| Keyword(4) | refresh |
| 1st Author's Name | Hiroshi Ito |
| 1st Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company() |
| 2nd Author's Name | Satoru Takase |
| 2nd Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company |
| 3rd Author's Name | Natsuki Kushiyama |
| 3rd Author's Affiliation | Microelectronics Engineering Laboratory, Toshiba Semiconductor Company |
| Date | 1999/5/27 |
| Paper # | ICD99-20 |
| Volume (vol) | vol.99 |
| Number (no) | 93 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |