Electronics-Integrated Circuits and Devices(Date:1999/03/04)

Presentation
表紙

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[Date]1999/3/4
[Paper #]
目次

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[Date]1999/3/4
[Paper #]
A Power Optimization Technique for Application Specific Memory Designs

Tohru ISHIHARA,  Hiroto YASUURA,  

[Date]1999/3/4
[Paper #]ICD-98-287
A Design Tool of Sequence Hardware Realized on FPGA with Functor Language

Takashi NISHIDA,  Masaaki NIIMURA,  Yasushi FUWA,  

[Date]1999/3/4
[Paper #]ICD-98-288
A Dynamic Reconfigurable System Based on Multiple FPGAs and Its Applications

Yohei HASEGAWA,  Nozomu TOGAWA,  Masao YANAGISAWA,  Tatsuo OHTSUKI,  

[Date]1999/3/4
[Paper #]ICD-98-289
Acceleration of Linear Block Code Evaluations Using Reconfigurable Hardware

Hidehisa Nagano,  Takayuki Suyama,  Akira Nagoya,  

[Date]1999/3/4
[Paper #]ICD-98-290
Hardware Generation from C Programs Based on the Optimization of Bit Length of Variables

Osamu Ogawa,  Kazuyoshi Takagi,  Yasufumi Itoh,  Shinji Kimura,  Katsumasa Watanabe,  

[Date]1999/3/4
[Paper #]ICD-98-291
Data Path Synthesis for Minimizing Scan Registers

Yuuichiro Shimizu,  Mineo Kaneko,  

[Date]1999/3/4
[Paper #]ICD-98-292
Assignment Based Approach to High Level Synthesis for NetRelevant Dsign Criteria

Yoshitaka Nishio,  Mineo Kaneko,  Satoshi Tayu,  

[Date]1999/3/4
[Paper #]ICD-98-292
C-based Hardware Design Methodology : With a Behavior Synthesizer, "Cyber" ()

Kazutoshi WAKABAYASHI,  

[Date]1999/3/4
[Paper #]ICD-98-294
()How the design methodology in the system-on-silicon era should be? : Toward the fusion of LSI design and system design

Toshinori SUEYOSHI,  Kiyoshi OGURI,  Kiichiro TAMARU,  Tetsuo HIRONAKA,  Kazutoshi WAKABAYASHI,  

[Date]1999/3/4
[Paper #]ICD-98-295
[OTHERS]

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[Date]1999/3/4
[Paper #]