Electronics-Integrated Circuits and Devices(Date:1996/05/23)

Presentation
表紙

,  

[Date]1996/5/23
[Paper #]
目次

,  

[Date]1996/5/23
[Paper #]
[CATALOG]

,  

[Date]1996/5/23
[Paper #]
High-Speed Sense Circuit Techniques for a 1Mb BiCMOS Cache SRAM

Akihiko Emori,  Kunihiko Suzuki,  Seigoh Yukutake,  Sadayuki Ookuma,  Kinya Mitumoto,  Takashi Akioka,  Masahiro Iwamura,  Noboru Akiyama,  

[Date]1996/5/23
[Paper #]ICD96-28
A 500MHz Synchronous Pipelined 1Mbit CMOS SRAM

T. Higuchi,  T. Miyabo,  S. Mabuchi,  T. Koga,  M. Matsumiya,  

[Date]1996/5/23
[Paper #]ICD96-29
0.25μmCMOS / SRAM / 500MHz / CACHE

Hiroshi Shimizu,  Kazuto Furumochi,  Masatoshi Fujita,  Tamiji Akita,  Tetsuo Izawa,  Masaki Katsube,  Keizo Aoyama,  Seiichiro Kawamura,  

[Date]1996/5/23
[Paper #]ICD96-30
A 1-V 100-MHz 10-mW Cache Using a Separated Bit-Line Memory Hierarchy Architecture and Domino Tag Comparators

Hiroyuki Mizuno,  Nozomu Matsuzaki,  Kenichi Osada,  Toshinobu Shinbo,  Nagatoshi Ooki,  Hiroshi Ishida,  Koichiro Ishibashi,  Tokuo Kure,  

[Date]1996/5/23
[Paper #]ICD96-31
Low-power First-in First-out Memories using Look-ahead-controlled Bitline Pull-up's

Nobutaro SHIBATA,  Mayumi WATANABE,  

[Date]1996/5/23
[Paper #]ICD96-32
A Mixed-Mode Voltage-Down Converter with impedance Adjustment Circuitry for Low-Voltage Wide-Frequency DRAMs

Tsukasa Ooishi,  Yuichiro Komiya,  Kei Hamade,  Mikio Asakura,  Kenichi Yasuda,  Kiyohiro Furutani,  Tetsuo Kato,  Hideto Hidaka,  Hideyuki Ozaki,  

[Date]1996/5/23
[Paper #]ICD96-33
1GビットDRAM用トレンチ・セル技術

,  

[Date]1996/5/23
[Paper #]ICD96-34
A 1.6G Byte/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture

Narumi Sakashita,  Yasuhiko Nitta,  Fumihiro Okuda,  Ken'ichi Shimomura,  Hiroki Shimano,  Masaki Tsukude,  Kazutami Arimoto,  Shinji Baba,  Shinji Komori,  Kazuo Kyuma,  Haruhiko Abe,  

[Date]1996/5/23
[Paper #]ICD96-35
[OTHERS]

,  

[Date]1996/5/23
[Paper #]