| Presentation | 1996/5/23 A 1-V 100-MHz 10-mW Cache Using a Separated Bit-Line Memory Hierarchy Architecture and Domino Tag Comparators Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ooki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 1-V 16-KB (L2) 2-KB (L1) 4-way set-associative cache was fabricated using a 0.25-μm CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9ns and power consumption of 10mW at 100MHz are obtained at a supply voltage of 1V. This performance is achieved by using a new separated bit-line memory hierarchy architecture that speeds up latency and reduces power consumption, and domino tag comparators that reduce the power dissipation of tag comparisons. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Microprocessor / RISC / Cache / SRAM / Low-Power |
| Paper # | ICD96-31 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 1996/5/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 1-V 100-MHz 10-mW Cache Using a Separated Bit-Line Memory Hierarchy Architecture and Domino Tag Comparators |
| Sub Title (in English) | |
| Keyword(1) | Microprocessor |
| Keyword(2) | RISC |
| Keyword(3) | Cache |
| Keyword(4) | SRAM |
| Keyword(5) | Low-Power |
| 1st Author's Name | Hiroyuki Mizuno |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Nozomu Matsuzaki |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 3rd Author's Name | Kenichi Osada |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 4th Author's Name | Toshinobu Shinbo |
| 4th Author's Affiliation | Hitachi ULSI Engineering Corp. |
| 5th Author's Name | Nagatoshi Ooki |
| 5th Author's Affiliation | Hitachi ULSI Engineering Corp. |
| 6th Author's Name | Hiroshi Ishida |
| 6th Author's Affiliation | Hitachi ULSI Engineering Corp. |
| 7th Author's Name | Koichiro Ishibashi |
| 7th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 8th Author's Name | Tokuo Kure |
| 8th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| Date | 1996/5/23 |
| Paper # | ICD96-31 |
| Volume (vol) | vol.96 |
| Number (no) | 64 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |