Presentation	1996/5/23 Low-power First-in First-out Memories using Look-ahead-controlled Bitline Pull-up's Nobutaro SHIBATA, Mayumi WATANABE,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Low-power circuit techniques suitable for sequential access memories are described. Two-port memory cells using PMOS transfer gates for read port and look-ahead-controlled bitline pull-up's reduce the power dissipation with no access-time penalty. The memory array architecture limiting the number of memory cells linked on write-port bitlines enables to remove the pull-up MOSFET's statically consuming electric power. The low power dissipation of 56-mW at 140-MHz operation was demonstrated by a first-in first-out memory (2K-word X 8-bit organization) fabricated with a 0.5-um CMOS process.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	ASIC / macrocell / FIFO / two-port / low-power / fast
Paper #	ICD96-32
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Conference Information
Committee	ICD
Conference Date	1996/5/23(1days)
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Place (in English)
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Topics (in English)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Low-power First-in First-out Memories using Look-ahead-controlled Bitline Pull-up's
Sub Title (in English)
Keyword(1)	ASIC
Keyword(2)	macrocell
Keyword(3)	FIFO
Keyword(4)	two-port
Keyword(5)	low-power
Keyword(6)	fast
1st Author's Name	Nobutaro SHIBATA
1st Author's Affiliation	NTT LSI Laboratories()
2nd Author's Name	Mayumi WATANABE
2nd Author's Affiliation	NTT LSI Laboratories
Date	1996/5/23
Paper #	ICD96-32
Volume (vol)	vol.96
Number (no)	64
Page	pp.pp.-
#Pages	8
Date of Issue