Information and Systems-Reconfigurable Systems(Date:2017/11/06)

Presentation
Real Chip Evaluation of a Variable Pipelined Coarse-Grained Reconfigurable Array

Naoki Ando(Keio Univ.),  Takuya Kojima(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2017-11-07
[Paper #]RECONF2017-40
On Avoiding Test Data Corruption by Optimal Scan Chain Grouping

Yucong Zhang(KIT),  Stefan Holst(KIT),  Xiaoqing Wen(KIT),  Kohei Miyase(KIT),  Seiji Kajihara(KIT),  Jun Qian(AMD),  

[Date]2017-11-07
[Paper #]VLD2017-42,DC2017-48
Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch

Tetsuaki Fujimoto(Ritsumeikan Univ.),  Wataru Takahashi(NEC),  Kazutoshi Wakabayashi(NEC),  Takashi Imagawa(Ritsumeikan Univ.),  Hiroyuki Ochi(Ritsumeikan Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-38,DC2017-44
A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication

Takashi Imagawa(Ritsumeikan Univ.),  Takahiro Ikeshita(Hokkaido Univ.),  Hiroshi Tsutsui(Hokkaido Univ.),  Yoshikazu Miyanaga(Hokkaido Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-45,DC2017-51
Routing method considering programming constraint of reconfigurable device using via-switch crossbars

Kosei Yamaguchi(Ritsumeikan Univ.),  Takashi Imagawa(Ritsumeikan Univ.),  Hiroyuki Ochi(Ritsumeikan Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-39,DC2017-45
A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Oscillator Circuit

Yuki Tanaka(Kyoto Univ.),  Song Bian(Kyoto Univ.),  Masayuki Hiromoto(Kyoto Univ.),  Takashi Sato(Kyoto Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-40,DC2017-46
暗号回路に挿入されたハードウェアトロイとその抑止回路のFPGA実装

Kento Hasegawa(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-52,DC2017-58
大規模マルチFPGAシステムでの深層学習アクセラレート

Kazusa Musha(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2017-11-07
[Paper #]CPSY2017-40
Calculation method of exponential function on FPGAs using high-radix STL method

Yasufumi Fujiwara(Kyoto Univ.),  Kazuyoshi Takagi(Kyoto Univ.),  Naofumi Takagi(Kyoto Univ.),  

[Date]2017-11-07
[Paper #]RECONF2017-46
Design to Improve Open Defect Detection for Test Based on IDDT Appearance Time

Ayumu Kambara(Tokushima Univ.),  Kouhei Ohtani(Tokushima Univ.),  Hiroyuki Yotsuyanagi(Tokushima Univ.),  Masaki Hashizume(Tokushima Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-49,DC2017-55
Design of Weak-Signal-Readout-System for Terahertz-Video-Imaging

Toshiyuki Kikkawa(The Univ. of Tokyo),  Makoto Ikeda(The Univ. of Tokyo),  

[Date]2017-11-07
[Paper #]CPM2017-83,ICD2017-42,IE2017-68
DCNN Training with Short Bit Length Format Considering Loss of Trailing Digits

Shin-ichi O'uchi(AIST),  Hiroshi Fuketa(AIST),  Ryousei Takano(AIST),  

[Date]2017-11-07
[Paper #]CPSY2017-41
Zynq上のプロセッサ‐ロジック間のストリーム接続のトレードオフ評価

Daiki Kunikawa(Ritsumeikan Univ.),  Kazuki Komori(Ritsumeikan Univ.),  Tomonori Izumi(Ritsumeikan Univ.),  

[Date]2017-11-07
[Paper #]RECONF2017-47
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table

Yuji Shindo(TCU),  Kenshu Seto(TCU),  Hao San(TCU),  

[Date]2017-11-07
[Paper #]VLD2017-44,DC2017-50
A Low-Voltage Operation Self-Calibration Hysteresis Comparator

Takumi Saito(TDU),  Satoshi Komatsu(TDU),  

[Date]2017-11-07
[Paper #]CPM2017-80,ICD2017-39,IE2017-65
Real chip evaluation of a low-power overhead body bias controller

Hayate Okuhara(Keio Univ.),  Akram BenAhmed(Keio Univ.),  Hideharu Amano(Keio Univ.),  

[Date]2017-11-07
[Paper #]CPM2017-81,ICD2017-40,IE2017-66
Stochastic logic circuit using static constant as coefficient without random number generator

Masashi Tawada(Waseda Univ.),  Masao Yanagisawa(Waseda Univ.),  Nozomu Togawa(Waseda Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-48,DC2017-54
[Invited Talk] Application of Real-time Image Recognition System with Machine and Transfer Learnings to Computer-Aided Diagnosis for Endoscopic Images of Colorectal Cancer

Tetsushi Koide(Hiroshima Univ.),  Toru Tamaki(Hiroshima Univ.),  Shigeto Yoshida(Medical Corp. JR Hiroshima Hospital),  Hiroshi Mieno(Medical Corp. JR Hiroshima Hospital),  Shinji Tanaka(Hiroshima Univ. Hospital),  

[Date]2017-11-07
[Paper #]CPSY2017-42
On low power oriented test pattern compaction using SAT solver

Yusuke Matsunaga(Kyushu Univ.),  

[Date]2017-11-07
[Paper #]VLD2017-43,DC2017-49
CPU-FPGAクラスタのデータ転送機構の実装と性能評価

Yohei Sakamoto(Univ. of the Ryukyus),  Shuna Maehara(Univ. of the Ryukyus),  Yasunori Osana(Univ. of the Ryukyus),  

[Date]2017-11-07
[Paper #]RECONF2017-48
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